CPU

9 replies [Last post]
Offline
Joined: Aug 12 2015
Posts: 171

I read this today

In fact, the Apple II did two memory accesses per cycle, two million per second at 1MHz, with the video accessing the memory during
the first half of Φ2, and the processor during the second half, interleaving, so both could access the same memory at the same time
at full speed, with no conflicts.

Any idea from what Apple II book this is from?

Here is the webpage

http://wilsonminesco.com/6502primer/addr_decoding.html

Comment viewing options

Select your preferred way to display the comments and click "Save settings" to activate your changes.
resman's picture
Offline
Joined: Feb 9 2006
Posts: 214
Re: CPU

There are probably a handful of books that describe the clever video architecture of the Apple II, but this may be the most comprehensive: https://archive.org/details/understanding_the_apple_ii

Offline
Joined: Aug 12 2015
Posts: 171
Re: CPU

I found a lead in here.
It's in the Apple IIe Reference Manual Page 149 in
RAM Addressing.

The memory circuits in the Apple IIe take advantage of the
two phase system clock described in the section "System Timing"
to interleave the microprocessor memory accesses and the display
memory accesses so that they never interfere with each other. The
microprocessor reads or writes to RAM only during phase 0, and
the display circuits read data only during phase 1.

Except I had a look and there is no section "System Timing"

speedyG's picture
Offline
Joined: Nov 16 2011
Posts: 2415
Re: CPU

It reaally does seem that previous given advices to read have not been treated seriously....:

http://www.applefritter.com/?q=content/irq
#3:

Quote:

"and seond the handling of "switched memory" caused by the adressing limits of the Apple II series to 64kB
and the 128 kB limitation at the IIe and finally the 16 MB at the IIGS - switching portions of the expanded video-memory to the
lower 64 kB portion of memory for the Videodisplay....which is also related to the handling of Interupts...
therefor i urgently recomend to read first the books:
WINSTON GAYLOR - the Apple II circuit description
then continue with:
JIM SATHER - understanding the IIe
to understand the topic itself and the related topics..."

otherwise - if the books have been acknowledged this thread would have not been started this way...
just to repeat the advice:
WINSTON GAYLOR - the Apple II circuit description >>
http://mirrors.apple2.org.za/Apple%20II%20Documentation%20Project/Books/W.%20Gayler%20-%20The%20Apple%20II%20Circuit%20Description.pdf
Chapter 4 + 5 +8
pages 34 ff
+
pages 104 ff
+
pages 185 ff

JIM SATHER - understanding the IIe >>
http://mirrors.apple2.org.za/Apple%20II%20Documentation%20Project/Books/Jim%20Sather%20-%20Understanding%20the%20Apple%20II.pdf
Chapter 4 +5 +7 +8
starting at pages 15 ff
starting at pages 35 ff
starting at pages 61 ff

Not to forget:
Gary B. Little -Inside the //e
>>
mirrors.apple2.org.za/Apple%20II%20Documentation%20Project/Books/Gary%20B.%20Little%20-%20Inside%20the%20IIe.pdf
starting at pages 279 ff
....

reading helps...and can realy increase knowledge

sincerely
SpeedyG

__________________

In early days I had a lot of money but no time - now I have no money but a lot of time....
the second part includes less friends but a lot more joy on life....

Offline
Joined: Aug 12 2015
Posts: 171
Re: CPU

reading helps...and can realy increase knowledge

Take your own advice and read what I wrote in the first post.
You are not reading the posts as they are posted.

In fact, the Apple II did two memory accesses per cycle, two million per second at 1MHz, with the video accessing the memory during
the first half of Φ2, and the processor during the second half, interleaving, so both could access the same memory at the same time
at full speed, with no conflicts.

I then found it in the Apple IIe Reference Manaul.

It's in the Apple IIe Reference Manual Page 149 in
RAM Addressing.

The memory circuits in the Apple IIe take advantage of the
two phase system clock described in the section "System Timing"
to interleave the microprocessor memory accesses and the display
memory accesses so that they never interfere with each other. The
microprocessor reads or writes to RAM only during phase 0, and
the display circuits read data only during phase 1.

Except I had a look and there is no section "System Timing"

You then put this quote in your post.

"and seond the handling of "switched memory" caused by the adressing limits of the Apple II series to 64kB
and the 128 kB limitation at the IIe and finally the 16 MB at the IIGS - switching portions of the expanded video-memory to the
lower 64 kB portion of memory for the Videodisplay....which is also related to the handling of Interupts...
therefor i urgently recomend to read first the books:
WINSTON GAYLOR - the Apple II circuit description
then continue with:
JIM SATHER - understanding the IIe
to understand the topic itself and the related topics..."

This is not related to the question I put up about "System Timing"
and interleaving. Again you need to read and keep up what the
posts are saying.

You then mention a previous post I had put up and books that I need
to read. They do not explain interleaving.

If you are going to recommend a book, make sure that it answers
the question I have specifically asked instead of just of
it's in that book you need to read it.

speedyG's picture
Offline
Joined: Nov 16 2011
Posts: 2415
Re: CPU

The reply is perfect proof that you neither read the one book nor the other.

__________________

In early days I had a lot of money but no time - now I have no money but a lot of time....
the second part includes less friends but a lot more joy on life....

Offline
Joined: Aug 12 2015
Posts: 171
Re: CPU

The quote from the website looks like a mystery.
I asked the author of the website and he didn't
know where it came from. (strange)

This theme was looked into at Kansas Fest 2011
in which a video was done.

Here is the video

https://www.youtube.com/watch?v=LP5k15g_0AM

It is not listed in the Apple II Circuit Description
Pages as Speedy G has suggested.
The book does take an approach of detailed analysis
of the Apple II so I will have to read the whole
book to see if the quote is correct.

speedyG's picture
Offline
Joined: Nov 16 2011
Posts: 2415
Re: CPU

Quote:

from you:
t's in the Apple IIe Reference Manual Page 149 inRAM Addressing.

The memory circuits in the Apple IIe take advantage of the
two phase system clock described in the section "System Timing"
to interleave the microprocessor memory accesses and the display
memory accesses so that they never interfere with each other. The
microprocessor reads or writes to RAM [u]only during phase 0
, and
the display circuits read data only during phase 1.[/u]

Quote:

citation from WINSTON GAYLOR - the Apple II circuit description:

Read Cycle -Fig. 5-3 shows the t irn ing of memory read-cycles. Note how video
and 6502 cycles are interleaved. Signal L.OPS rising at point A advances the video
address at point B. With (/>O low and AX high, the row bits of the video address are
Read Cycle -Fig. 5-3 shows the timing of memory read-cycles. Note how video
and 6502 cycles are interleaved. Signal L.OPS rising at point A advances the video
address at point B. With (/>O low and AX high, the row bits of the video address are
Recall from the clock discussion in Chapter 3 that every 65th cPO· period is extended
by 140 nS. We have drawn Fig. 5-3 to represent a RAM read cycle without
this extension. At the bottom of the figure we have indicated the location for the
extension. All the waveforms from Fig. 5-3 are redrawn .in Fig. 5-4 with the 140 nS
extension added. Even though the timing is altered, the extended cycle of Fig. 5-4
functions just like the normal cycle of Fig. ,5-3.
Write Cycle -Fig. 5-5 shows a RAMI write cycle. It is interleaved between two
video cycles just like the 6502 read cycle of Fig. 5-3.. ·The video cycles are the same as
described previously. (Note that video cycles always read .from RAM.) On a write
cycle, the address is strobed into RAM the same as on a read cycle. The address is
divided into row and column bits at points A and B (Fig. 5-5) and these are strobed
at points C and D. Since this is a write cycle, the 6502 takes RJW low at about point
E. When cP1"falls at point F, 4116 WR goes low (point G). Since ·WR goes low 'before
CAS, the 4116 will enter an early-write cycle when CAS falls at point D. Meanwhile,
the 6502 has output the data to be written at about point H. This data is driven onto
the data bus and becomes stable at point I. The data bus is connected directly to the
RAM inputs, so when CAS falls at point D, the data at point I is written into the
RAM. Note that in a 4116 early-write cycle, the 4116 data out pin remains high
impedance, point J.
Write cycles can be extended 140 nS just like read cycles. At the bottom of Fig.
5-5 we indicate where the extra 140 nS go.
Chapter 6 will discuss RAM read and write cycles again from the viewpoint of
the 6502.
Fig. 5-6 is a block diagram of the hardware process that occurs when we write to a
video screen location. Say we want to write the pixel that is ~~2 down and 3 over" (we
are being very general here). We have looked in the Apple II Reference Manual and
found the "address" of that pixel. What we have found is the location in RAM that
corresponds to that pixel. The address from the Apple II Reference Manual is what
the 6502 should put on the address bus to access that location. NO\\T let's examine
Fig. 5-6 to see what happens in the hardware. The 6502 puts the address on the
address bus, puts the data (on, off, blue, green, etc.: on the data bus, and performs a
RAM write cycle. On such a cycle, the address multiplexer selects the address bus.

Quote:

Fig. 5-6 is a block diagram of the hardware process that occurs when we write to a
video screen location. Say we want to write the pixel that is ~~2 down and 3 over" (we
are being very general here). We have looked in the Apple II Reference Manual and
found the "address" of that pixel. What we have found is the location in RAM that
corresponds to that pixel. The address from the Apple II Reference Manual is what
the 6502 should put on the address bus to access that location. NO\\T let's examine
Fig. 5-6 to see what happens in the hardware. The 6502 puts the address on the
address bus, puts the data (on, off, blue, green, etc.: on the data bus, and performs a
RAM write cycle. On such a cycle, the address multiplexer selects the address bus.

Quote:

then you reply:
This is not related to the question I put up about "System Timing"
and interleaving.
Again you need to read and keep up what the
posts are saying.
You then mention a previous post I had put up and books that I need
to read. They do not explain interleaving.???
If you are going to recommend a book, make sure that it answers
the question I have specifically asked instead of just of
it's in that book you need to read it.

Quote:

my reply:
The reply is perfect proof that you neither read the one book nor the other.

Quote:

And now you switch to a complete other TOPIC !:
This theme was looked into at Kansas Fest 2011
in which a video was done.
Here is the video
https://www.youtube.com/watch?v=LP5k15g_0AM
- a video about Apple IIgs System Timing and the FPI ?!

It is not listed in the Apple II Circuit Description
Pages as Speedy G has suggested.
Insert: Of course not ! Thats about the system timimng in the IIGS [b]by use of the FPI !
Its not about the interleave at the Apple II !!![/b]

great - mixing tomatoes and grapes.... but far off attiotude...
fare well...

__________________

In early days I had a lot of money but no time - now I have no money but a lot of time....
the second part includes less friends but a lot more joy on life....

Offline
Joined: Aug 12 2015
Posts: 171
Re: CPU

My initial post and question was this.

In fact, the Apple II did two memory accesses per cycle, two million per second at 1MHz, with the video accessing the memory during
the first half of Φ2, and the processor during the second half, interleaving, so both could access the same memory at the same time
at full speed, with no conflicts.

Any idea from what Apple II book this is from?

Your answer was

It reaally does seem that previous given advices to read have not been treated seriously....:

This was a new topic and discussion, but you have held over from a previous thread
that I should have read the books as the answer was in there.
You then re-repeated I should I read these books but gave the following pages.

WINSTON GAYLOR - the Apple II circuit description

Chapter 4 + 5 +8
pages 34 ff
+
pages 104 ff
+
pages 185 ff

These pages did not mention what I quoted.It was at that stage that I thought,
I have asked a question and he has advised me to read this book, so I decided
to read the pages he has now suggested and there still is no mention of what I was
talking about.

The memory circuits in the Apple IIe take advantage of the
two phase system clock described in the section "System Timing"
to interleave the microprocessor memory accesses and the display
memory accesses so that they never interfere with each other. The
microprocessor reads or writes to RAM only during phase 0, and
the display circuits read data only during phase 1.

Except I had a look and there is no section "System Timing"

I did not switch to another topic as the Apple IIe book
described "System Timing" which included interleaving but
there is not section included.

As I am looking for information that is scattered on the internet,
I remembered the Apple IIGS system video which is in my
topic of interleaving/System timing.

I am not aware that these are independent topics and not related.
If you are so knowledgeable about the Apple II series then
why don't you share this information.

I don't claim to be an expert but am asking questions.
Why don't you write a book then explaining all these
terms so everyone can benefit.

gsmcten's picture
Offline
Joined: Oct 4 2005
Posts: 2628
Re: CPU: "Resumes and Shoe-Leather"

I was not about to put in my two-cents, but...

The internet; as we know it, is really not that old.
A lot of us that started with computers in the very late '60's, '70's,
and '80's, did not have the luxury of "Instant Contact" with other
computer hobbyist's. Even in the '90's the Internet was unreliable and contacts were difficult.
We read Magazines, Books, Newspaper Articles, and anything we could
get our hands on for information.

We used "Snail-Mail", and Dial Telephones to contact folks who could
possibly; just possibly, help us get the information we were hungry for.

It was exactly the same for the Job Market.
Do you actually think that people used Job Websites then?

The process was called "Resumes and Shoe-Leather":

You found a job you were interested in.
You wrote your Resume using a Typewriter.
You reviewed your resume for mistakes. (Sometimes more than once)
You retyped the resume into its Final Form.
You then called the Personnel Department of the Company you were interested in to make an Appointment for an Interview.
You dressed in a Two, or Three-Piece Suit.
You drove, or walked (Shoe-Leather) to the company Headquarters.
You were at least 15 minutes early.
Whoever interviewed you would, some times, make copies of your Resume (WHAT??? You forgot to get a Mimeograph machine to make copies???),bring in several other people in the Department you were aiming for, so they could ask you questions.
They would invariably all say " Thank you for coming in. We will contact you with our decision."

But wait a minute.
You think that this is happening for just One Job?
Oh No!
You have at least 10 to 12 Interviews scheduled for just this week alone.
That is just 10 to twelve DIFFERENT RESUMES (Plus Copies).
Why?
Because each Company has a DIFFERENT RESUME STYLE.
That means you have to make your resume fit their style.

Now imagine doing this 10 to 12 Resumes a week for six months, just to have the possibility of getting the job you want?

Boiling it down:

"Resumes and Shoe-Leather" is still out there, right beside and a little back to the left, of all the new Job Sites.
The Internet is a wonderful device. It can give you Instant Gratification of a need or want.
But there are many of us who are considered "Old School".
I am considered one of the "Old-Timers".
I will search for things I want to know in unusual places.
I will also try my best to help other people who seek information, whatever the form.

I want to wish everyone a "Happy Holiday Season!"

"God Bless Us, Everyone."

Tiny Tim

Steven Smile
[/b]

(I guess this amounts to about $5.00 lol)

__________________

Steven (gsmcten)

"Apple ][.....It's ALIVE!!!!!"