; ============================================================================
; Applied Engineering Serial Pro v2.0 - structured disassembly (work in progress)
; ============================================================================
;
; Source basis:
;   Raw linear disassembly supplied from an AE Serial Pro v2.0 ROM dump.
;   Functional annotations are cross-checked against the supplied Serial Pro
;   User's Manual v2.0 transcription.
;
; IMPORTANT ADDRESS-MAPPING NOTE:
;   ORG $C800 is retained only to reproduce the supplied raw disassembly byte
;   stream. It is NOT a claim that all physical EPROM bytes are simultaneously
;   mapped linearly at Apple II $C800-$CFFF.
;
;   The v2.0 manual explicitly documents:
;       $C086 + $s0  EPROM Bank Register Clear (write only)
;       $C087 + $s0  EPROM Bank Register       (write only)
;
;   and separately documents slot-page firmware entry points at $Cs00, $Cs05,
;   $Cs07, $Cs11, Pascal 1.1 signature/offset bytes in $Cs0B-$Cs11, and firmware
;   revision at $CsFF. This proves that the Serial Pro uses banked/mapped EPROM
;   views rather than one simple linear $C800-$CFFF execution image.
;
;   For slot 2, the indexed hardware addresses become:
;       RTCSEL,Y   = $C0A4      6818 Clock/RAM address
;       RTCDATA,Y  = $C0A5      6818 Clock/RAM data
;       BANKCLR,Y  = $C0A6      EPROM Bank Register Clear
;       BANKREG,Y  = $C0A7      EPROM Bank Register
;       ACIADATA,Y = $C0A8      6551 DATA
;       ACIASTAT,Y = $C0A9      6551 STATUS/RESET
;       ACIACMD,Y  = $C0AA      6551 COMMAND
;       ACIACTRL,Y = $C0AB      6551 CONTROL
;
; Supplied byte range reconstructed here:
;   provisional CPU $C800-$CFFF
;   2048 bytes total.
;   Executable/data content ends at $CF35; $CF36-$CFFF is $FF fill.
;
; v1.4 -> v2.0 observations:
;   - Core initialization, terminal, serial, RTC and flow-control logic is
;     overwhelmingly conserved.
;   - v2.0 adds output-format handling around $CA4E-$CA60.
;   - command parsing now normalizes lowercase command letters.
;   - CommandTab gains four 3-byte records relative to the v1.4 image.
;   - several routines are refactored/relocated, but the same hardware model
;     and dynamic slot-page trampolines remain.
;
; ASM_core.js compatibility:
;   Uses EQU, ORG, standard legal 6502 mnemonics, HEX and .END only.
;   Overlapping instruction entry points are represented with EQU so their
;   underlying bytes are emitted once.
;
; Confidence wording:
;   Hardware-register meanings, battery-RAM meanings and documented public
;   entry points come from the v2.0 manual. Comments marked provisional,
;   likely or inferred are reverse-engineering hypotheses.
; ============================================================================

; ---------------------------------------------------------------------------
; Apple II / Serial Pro hardware symbols
; ---------------------------------------------------------------------------
KBD       EQU $C000
KBDSTRB   EQU $C010

RTCSEL    EQU $C084
RTCDATA   EQU $C085
BANKCLR   EQU $C086
BANKREG   EQU $C087
ACIADATA  EQU $C088
ACIASTAT  EQU $C089
ACIACMD   EQU $C08A
ACIACTRL  EQU $C08B

; ---------------------------------------------------------------------------
; Battery-backed 6818 RAM allocations documented by Serial Pro v2.0
; ---------------------------------------------------------------------------
BR_MODE       EQU $22       ; device type: communications/P8/printer/P8A
BR_CONTROL    EQU $23       ; saved 6551 CONTROL register image
BR_COMMAND    EQU $24       ; saved 6551 COMMAND register image
BR_LINE       EQU $25       ; printer line length
BR_DELAYCASE  EQU $26       ; case translation + CR/LF/FF delay flags
BR_HANDSHAKE  EQU $28       ; local echo, XON/XOFF, LF-after-CR
BR_GRAPHICS   EQU $29       ; graphics printer selection
BR_GFXCTL0    EQU $2B       ; graphics print control / scratch
BR_GFXCTL1    EQU $2C       ; graphics print control / scratch

; ---------------------------------------------------------------------------
; Apple II workspace / monitor symbols
; ---------------------------------------------------------------------------
CH        EQU $24
SLOTOFF   EQU $26
CHARBUF   EQU $27
BASL      EQU $28
CSWL      EQU $36
CSWH      EQU $37
KSWL      EQU $38
KSWH      EQU $39
A1L       EQU $3C
CNTLO     EQU $4E
CNTHI     EQU $4F
SLOTSAVE  EQU $07F8

NXTA1     EQU $FCBA
COUT1     EQU $FDF6

; Overlapping-code / alternate-map entry points.
AltLoad1  EQU $C8A0      ; bytes inside BIT $01A9 decode as LDA #$01
AltC8FA   EQU $C8FA      ; target enters a different/overlapping execution view
AltLoad0  EQU $CE11      ; bytes inside BIT $00A9 decode as LDA #$00

        ORG $C800


; ============================================================================
; SECTION 1 - EARLY ENTRY POINTS, EPROM BANKING, SLOT CONTEXT AND CONFIGURATION
; ============================================================================

;
; Pascal 1.0 initialization entry documented by the v2.0 manual. In this provisional host-ROM view
; it immediately jumps to BaseInit.
PascalInit
        JMP BaseInit
;
; EPROM-bank wrapper. The v2.0 manual identifies $C086+$s0 as Bank Register Clear and $C087+$s0 as
; the EPROM Bank Register. This routine selects a bank through BankSelect, then restores bank
; value $00.
BankCall
        PHP
        SEI
        LDA #$00
        PHA
        JSR BankSelect
        PLA
        LDY SLOTOFF
        STA BANKREG,Y                ; restore EPROM bank register to $00
        PLP
        RTS
;
; Write X to the EPROM Bank Register at $C087+slot offset. There is intentionally no RTS in this
; byte stream; subsequent instruction fetches depend on the selected bank/view.
BankSelect
        TXA
        LDY SLOTOFF
        STA BANKREG,Y                ; write X to EPROM bank register; selected bank changes following ROM view
;
; Base initialization in the currently visible bank: save slot context, load battery-backed
; configuration, then return X=0.
BaseInit
        JSR SaveCtx
        LDA #$16
        JSR LoadCfg
        LDX #$00
        RTS
;
; Secondary/status entry. Save context, query ACIA status and return a per-slot status/error value
; in X.
StatusEnt
        JSR SaveCtx
        LSR A
        JSR AciaTest
        LDA $05B8,X
        TAX
        RTS
;
; Maintain the firmware's per-slot column/count state from CHARBUF; printable characters and
; backspace-like controls take different paths.
TrackCol
        LDA CHARBUF
        ORA #$80
        CMP #$A0
        BCC LC840
        EOR #$FF
        BEQ LC844
        INC $06B8,X
        RTS
LC840
        EOR #$88
        BNE LC84C
LC844
        DEC $06B8,X
        BPL LC84C
        STA $06B8,X
LC84C
        RTS
;
; Pascal 1.0 read entry documented at $C84D. It obtains a character through ReadEntry and caches
; the resulting per-slot status.
PascalRead
        JSR ReadEntry
        LDX SLOTSAVE
        STA $05B8,X
        RTS
;
; Save card context. X is treated as the slot-page high byte $Cn; Y is retained as the slot I/O
; offset.
SaveCtx
        PHA
        STY SLOTOFF
        STX SLOTSAVE                 ; save slot-page high byte $Cn
        LDA #$00
        STA $05B8,X
        PLA
        RTS
;
; Load Serial Pro defaults from 6818 battery RAM and program the 6551. The v2.0 manual identifies
; RAM $22-$29, allowing several fields below to be named with high confidence.
LoadCfg
        PHA
        LDX #$01
        JSR BankCall
        LDX SLOTSAVE
        LDA #BR_HANDSHAKE            ; battery RAM $28 = handshake/default flags
        JSR RtcRead
        STA $0738,X
        LDA #BR_DELAYCASE            ; battery RAM $26 = CR/LF/FF delay + case-translation flags
        JSR RtcRead
        STA $03B8,X
        LDA #BR_MODE                 ; battery RAM $22 = device/mode byte
        JSR RtcRead
        BEQ AltLoad1
        LSR A
        BCC LC891
        LSR A
        LDA #$03
        BCS LC88E
        LDA #$80
LC88E
        STA $04B8,X
LC891
        LDA #BR_LINE                 ; battery RAM $25 = printer line length
        JSR RtcRead
        STA $0638,X
        PLA
        AND #$95
        PHA
        LDA #$09
        BIT $01A9
        STA $0538,X
        PLA
        ORA $0738,X
        STA $0738,X
        LDA #BR_CONTROL              ; battery RAM $23 -> 6551 CONTROL image
        JSR RtcRead
        STA ACIACTRL,Y               ; slot 2: $C0AB, 6551 CONTROL
        LDA #BR_COMMAND              ; battery RAM $24 -> 6551 COMMAND image
        JSR RtcRead
        STA ACIACMD,Y                ; slot 2: $C0AA, 6551 COMMAND
        LDA ACIADATA,Y               ; slot 2: $C0A8 DATA; read primes/clears receive state
        RTS
;
; Character-input entry used by the firmware core. Wait for input, strip bit 7 for internal
; processing, then run flow/setup logic.
ReadEntry
        JSR SaveCtx
        JSR WaitInput
        AND #$7F
        BCS LC8D2
LC8CA
        STA CHARBUF
        JSR SaveCtx
        JSR CheckFlow
LC8D2
        LDY SLOTSAVE
        LDX $05B8,Y
        RTS

; ============================================================================
; SECTION 2 - APPLE I/O VECTOR AND TERMINAL MODE SETUP
; ============================================================================

;
; BASIC I/O vector/mode setup. When this card already owns CSW/KSW, force the low bytes to
; documented BASIC entry offsets $07 (output) and $05 (input).
HookIO
        BVC LC908
        LDA $0538,X
        AND #$7F
        STA $0538,X
        LDA #$1F
        AND ACIACMD,Y
        BNE LC8EF
        LDA #$66
        JSR LoadCfg
LC8EF
        CPX CSWH                     ; compare current slot high byte with CSW high byte
        BNE LC8FD
        LDA #$07
        CMP CSWL
        BEQ LC8FD
        STA CSWL                     ; force BASIC output vector low byte to $07
        BNE LC90A
LC8FD
        CPX KSWH                     ; compare current slot high byte with KSW high byte
        BNE LC90A
        LDA #$05
        STA KSWL                     ; force BASIC input vector low byte to $05
LC905
        JMP InputLoop
LC908
        BCS LC905
LC90A
        JMP TermCore
;
; Update per-slot flow/mode flags from control characters in CHARBUF. Exact meanings of $92/$94
; remain provisional.
FlowFlags
        LDA $0738,X
        AND #$0A
        CMP #$0A
        BNE LC92A
        LDY CHARBUF
        LDA $04B8,X
        AND #$7F
        CPY #$92
        BEQ LC927
        ORA #$80
        CPY #$94
        BNE LC92A
LC927
        STA $04B8,X
LC92A
        RTS
PadC92B
; 18 zero bytes; alignment/unused space retained exactly.
        HEX 00000000000000000000000000000000
        HEX 0000

; ============================================================================
; SECTION 3 - BLOCK SERIAL TRANSFER
; ============================================================================

;
; Block serial transfer using Apple Monitor A1/A2. V selects serial->memory versus memory->serial.
BlockIO
        BIT $FF58
        BVC AltC8FA
        LDA #$00
        LDX SLOTSAVE
        STA $05B8,X
        TXA                          ; convert saved $Cn to slot I/O offset ($C2 << 4 -> $20)
        ASL A
        ASL A
        ASL A
        ASL A
        STA SLOTOFF
        BVC LC962
LC953
        JSR TryRx
        BCC LC953
        LDY #$00
        STA (A1L),Y                  ; received serial byte -> Apple Monitor A1 buffer
        JSR NXTA1                    ; advance A1 and compare with A2
        BCC LC953
        RTS
LC962
        LDY #$00
        LDA (A1L),Y                  ; Apple Monitor A1 buffer -> serial output
        STA CHARBUF
        JSR WaitTx                   ; wait for transmitter and send CHARBUF
        JSR NXTA1
        BCC LC962
        RTS

; ============================================================================
; SECTION 4 - TERMINAL CHARACTER STATE MACHINE
; ============================================================================

;
; Main terminal/character state machine: mode bits, flow control and input/output formatting.
TermCore
        LDA $04B8,X
        ASL A
        BPL LC989
        ROR A
        AND #$BF
        STA $04B8,X
        PLA
        PHA
        TAX
        LDA CHARBUF
        ORA #$20
        STA $0200,X
        STA CHARBUF
LC989
        JSR TestFlag2
        BEQ OutputFmt
        JSR CheckFlow
LC991
        JSR TestFlag2
        BEQ LC99E
        LDA $04B8,X
        BPL LC99E
        JSR LineMode
LC99E
        PLA
        TAX
LC9A0
        PLA
        TAY
        LDA CHARBUF
        RTS
PadC9A5
; 5 zero bytes; alignment/unused space retained exactly.
        HEX 0000000000
ResumeIn
        JMP LC8CA
;
; Input-side loop. Poll setup/keyboard/serial conditions and maintain per-slot terminal state.
InputLoop
        JSR TestFlag2
        BEQ LC9C1
        LDA $06B8,X
        BPL LC9BC
        LSR $06B8,X
        BNE LC9C6
LC9BC
        JSR SetupCheck
        BCS LC9CC
LC9C1
        JSR TryInput
        BCC LC9BC
LC9C6
        JSR StoreChar
        JSR FlowFlags
LC9CC
        LDA CHARBUF
        CMP #$E0
        BCC LC991
        LDA $03B8,X
        AND #$C0
        BEQ LC991
        LDA $04B8,X
        ORA #$40
        STA $04B8,X
        BNE LC991
;
; Output formatting path. Tracks line/column state and feeds characters through the serial-output
; pipeline.
OutputFmt
        JSR FlowCtrl
        BCS LC99E
        LDA CHARBUF
        PHA
        LDA $0738,X
        AND #$C0
        BNE LCA08
        LDA CH
        BEQ LCA29
        CMP #$08
        BEQ LC9FE
        CMP #$10
        BNE LCA08
LC9FE
        ORA #$F0
        AND $06B8,X
        CLC
        ADC CH
        STA CH
LCA08
        LDA $06B8,X
        CMP CH
        BEQ LCA29
        LDA #$A0
        BCC LCA1B
        LDA $0738,X
        ASL A
        BPL LCA29
        LDA #$88
LCA1B
        STA CHARBUF
        JSR TrackCol
        JSR ProcessOut
        JSR LCA75
        JMP LCA08
LCA29
        PLA
        JSR CharOut
        LDA $0738,X
        BMI LCA48
        LDY $06B8,X
        ASL A
        BMI LCA46
        TYA
        LDY #$00
        SEC
        SBC $0638,X
        CMP #$F8
        BCC LCA46
        ADC #$27
        TAY
LCA46
        STY CH
LCA48
        JMP LC99E
;
; Character-output preparation. v2.0 adds explicit bit-7 normalization based on format state
; before the common output path.
CharOut
        STA CHARBUF
        PHA
        LDA $04B8,X                  ; v2.0: examine output-format state bits 4-5
        AND #$30
        BEQ LCA61
        CMP #$20
        LDA CHARBUF
        AND #$7F                     ; v2.0: normalize outgoing data to 7 bits
        BCC LCA5F
        ORA #$80                     ; v2.0: optionally restore high bit according to format state
LCA5F
        STA CHARBUF
LCA61
        JSR OutPrep
        JSR TrackCol
        PLA
        STA CHARBUF
        EOR #$8D
        ASL A
        BNE LCA75
        STA $06B8,X
        STA CH
        RTS
LCA75
        LDA $04B8,X
        BPL LCA87
        LDA $0638,X
        BEQ LCA87
        CLC
        SBC $06B8,X
        LDA #$8D
        BCC CharOut
LCA87
        RTS
;
; Return Z according to bit 1 of the per-slot handshake/mode flags.
TestFlag2
        LDX SLOTSAVE
        LDA $0738,X
        AND #$02
        RTS
;
; Dispatch EPROM-bank/control operations according to incoming processor flags.
CtlDispatch
        BVS LCAA6
        BCC LCA9D
        LDX #$02
        JSR BankCall
        JMP LC99E
LCA9D
        LDX #$0A
        JSR BankCall
        PLA
        JMP LC9A0
LCAA6
        LDX #$12
        JSR BankCall
        JMP LC99E
;
; Issue bank/control operation $09 through BankCall.
Cmd09
        LDX #$09
        JSR BankCall
        RTS
;
; Screen/buffer processing path used by terminal mode.
LineMode
        LDA #$7F
        AND $0738,X
        STA $0738,X
        LDA #$00
LCABE
        PHA
LCABF
        JSR NextBuf
        PLA
        BCC LCAD3
        TAY
        JSR Translate
        TYA
        BCC LCABE
        PHA
        JSR OutPrep
        JMP LCABF
LCAD3
        JSR StoreChar
        LDA #$8D
        STA CHARBUF
        RTS
;
; Fetch current screen/buffer character via BASL/CH and apply flow/output processing.
NextBuf
        LDY CH
        LDA (BASL),Y
        STA CHARBUF
LCAE1
        LDA CNTHI
        AND #$03
        BNE LCAF5
        LDY CH
        LDA #$DF
        CMP (BASL),Y
        BNE LCAF1
        LDA CHARBUF
LCAF1
        STA (BASL),Y
        INC CNTHI
LCAF5
        LDA $04B8,X
        ASL A
        BCC LCB07
        JSR TryInput
        BCS LCB08
        JSR SetupCheck
        BCC LCAE1
        BVS NextBuf
LCB07
        RTS
LCB08
        JSR StoreChar
        JSR FlowFlags
        JSR DisplayChar
        JMP NextBuf
;
; Translate terminal escape/control input; CharMap handles special characters and alphabetic case
; conversion.
Translate
        LDA $0738,X
        ASL A
        BPL LCB47
        LDA CHARBUF
        CMP #$9B
        BNE LCB27
        DEY
        BPL LCB25
        LDY #$02
LCB25
        CLC
        RTS
LCB27
        CPY #$01
        BCC LCB47
        BEQ LCB39
        CMP #$C1
        BCC LCB47
        CMP #$DB
        BCS LCB47
        ORA #$20
        BNE LCB43
LCB39
        EOR #$B0
        CMP #$0B
        BCS LCB45
        TAY
        LDA $CB49,Y
LCB43
        STA CHARBUF
LCB45
        LDY #$02
LCB47
        SEC
        RTS
CharMap
; Special control/escape translation table used by Translate.
        HEX 9B9C9FDBDCDFFBFCFDFEFF
;
; Try to obtain a serial character. Success returns C=1; line-feed receives special handling.
TryInput
        JSR TryRx
        BCC LCB6A
        ORA #$80
        CMP #$8A
        BNE LCB69
        CLC
        LDA $0738,X
        AND #$20
        BNE LCB6A
        LDA #$8A
LCB69
        SEC
LCB6A
        RTS
;
; Flow-control recognizer. Uses persistent mode configuration and handles XON/XOFF/control-command
; state.
FlowCtrl
        LDA #BR_MODE
        JSR RtcRead
        LSR A
        BCS LCBAD
        LDA $04B8,X
        AND #$07
        BEQ LCB7F
        JSR CfgCommand
        SEC
        RTS
LCB7F
        LDA CHARBUF
        AND #$7F
        CMP $0538,X
        BNE LCB91
        INC $04B8,X
        TXA
        PHA                          ; push $Cn as dynamic slot-page target high byte
        LDA #$8F                     ; $8F + RTS increment => call slot-page $Cn90
        PHA
        RTS
LCB91
        LDA $0738,X
        AND #$08
        BEQ LCBAD
        JSR TryInput
        BCC LCBAD
        CMP #$93
        BEQ WaitCtl91
        PHA
        LDA $0738,X
        LSR A
        LSR A
        PLA
        BCC LCBAE
        STA $06B8,X
LCBAD
        CLC
LCBAE
        RTS
;
; Wait until control character $91 is received.
WaitCtl91
        JSR WaitInput
        CMP #$91
        BNE WaitCtl91
        CLC
LCBB7
        RTS
;
; Repeatedly call FlowCtrl until it reports completion.
CheckFlow
        JSR FlowCtrl
        BCS LCBB7
;
; Prepare CHARBUF for output, including optional control-panel/terminal handling.
OutPrep
        LDA $0738,X
        BPL ProcessOut
        JSR DisplayChar
;
; Main output-processing wrapper around serial transmit, post-character delay and escape handling.
ProcessOut
        LDA CHARBUF
        PHA
        LDA #BR_MODE
        JSR RtcRead
        CMP #$03
        BNE LCC16
        LDA $0438,X
        CMP #$99
        BCS LCBE8
        CMP #$95
        BCC LCBFE
        CMP #$96
        PLA
        PHA
        AND #$7F
        EOR #$1B
        BNE LCBFE
        BCC LCC01
LCBE8
        LDA $04B8,X
        AND #$1F
        ORA #$80
        STA CHARBUF
LCBF1
        JSR WaitTx
        JSR WaitInput
        EOR #$86
        BNE LCBF1
        STA $0438,X
LCBFE
        INC $0438,X
LCC01
        PLA
        PHA
        STA CHARBUF
        EOR #$8D
        ASL A
        BNE LCC16
        LDA $03B8,X
        AND #$30
        BEQ LCC16
        LDA #$C8
        STA $0438,X
LCC16
        JSR WaitTx
        JSR PostDelay
        LDA $0738,X
        LSR A
        LDA CHARBUF
        ROL A
        CMP #$1B
        BNE LCC2E
        LDA #$8A
        STA CHARBUF
        JSR ProcessOut
LCC2E
        PLA
        STA CHARBUF
        RTS
;
; Store CHARBUF in the current BASL/CH position and apply low-control-character translation when
; configured.
StoreChar
        PHA
        LDY CH
        LDA CHARBUF
        STA (BASL),Y
        PLA
        CMP #$95
        BNE LCC51
        LDA CHARBUF
        CMP #$20
        BCS LCC51
        LDY $03B8,X
        BPL LCC51
        EOR #$C0
        CPY #$C0
        BCS LCC51
        EOR #$20
LCC51
        STA CHARBUF
        RTS

; ============================================================================
; SECTION 5 - LOW-LEVEL SERIAL, RTC AND KEYBOARD PRIMITIVES
; ============================================================================

;
; Wait for an input character, polling the keyboard when serial input is not yet available.
WaitInput
        JSR TryInput
        BCS LCC5E
        JSR KeyPoll
        BCC WaitInput
LCC5E
        RTS
;
; 6818 clock/battery-RAM read primitive: A selects a clock/RAM register, then the value is read
; through $C085+slot offset.
RtcRead
        PHP
        SEI
        LDY SLOTOFF
        STA RTCSEL,Y                 ; slot 2: $C0A4, 6818 address register
        LDA RTCDATA,Y                ; slot 2: $C0A5, 6818 data/RAM register
        PLP
        ORA #$00
        RTS
;
; Wait for 6551 transmitter-ready status, then arrange the firmware return path with CHARBUF in A.
WaitTx
        CLC
        JSR AciaTest
        BCC WaitTx
        TXA
        PHA
        LDA #$8B
        PHA
        LDA CHARBUF
        RTS
;
; Read 6551 DATA only when AciaTest reports receive data available.
TryRx
        SEC
        JSR AciaTest
        BCC LCC84
        LDA ACIADATA,Y               ; slot 2: $C0A8, 6551 DATA
LCC84
        RTS
;
; Low-level 6551 STATUS interpreter. Carry on entry selects receive-ready versus transmit-ready
; interpretation.
AciaTest
        LDY SLOTOFF
        LDA ACIASTAT,Y               ; slot 2: $C0A9, 6551 STATUS/RESET
        BCC LCCA4
        AND #$2F
        CMP #$20
        BCC LCC98
        CMP #$28
        ORA #$08
        BNE LCCA0
LCC98
        CMP #$08
        AND #$07
        BEQ LCCA3
        ORA #$20
LCCA0
        STA $05B8,X
LCCA3
        RTS
LCCA4
        AND #$70
        CMP #$10
        BEQ LCCAB
        CLC
LCCAB
        RTS
;
; Poll Apple keyboard when keyboard input is enabled in firmware state.
KeyPoll
        CLC
        LDA $0738,X
        AND #$04
        BEQ LCCBD
        LDA KBD                      ; Apple keyboard data/strobe
        BPL LCCBD
        STA KBDSTRB                  ; clear Apple keyboard strobe
        SEC
LCCBD
        RTS

; ============================================================================
; SECTION 6 - BUILT-IN SETUP / CONTROL PANEL
; ============================================================================

;
; Built-in setup/control-panel trigger and command loop. v2.0 consolidates trigger recognition
; through FlowCtrl before printing the AE PRO: prompt.
SetupCheck
        INC CNTLO
        BNE LCCC4
        INC CNTHI
LCCC4
        JSR KeyPoll
        CLV
        BCC LCD09
        JSR StoreChar
        JSR FlowCtrl
        BCC LCD08
LCCD2
        LDY #$07
LCCD4
        LDA $CD0A,Y                  ; read reverse-stored <CR>AE PRO: prompt
        STA CHARBUF
        TYA
        STA KBDSTRB
        PHA
        JSR DisplayChar
        PLA
        TAY
        DEY
        BPL LCCD4
LCCE6
        LDA KBD
        BPL LCCE6
        STA KBDSTRB
        CMP #$88
        BEQ LCCD2
        STA CHARBUF
        JSR DisplayChar
        JSR FlowCtrl
        LDA $04B8,X
        AND #$07
        BNE LCCE6
        LDA #$8D
        STA CHARBUF
        BIT $FF58
LCD08
        SEC
LCD09
        RTS
AePrompt
; Reverse-stored high-bit Apple text. Read from end to start: <CR>AE PRO:.
        HEX BACFD2D0A0C5C18D
;
; Display/echo CHARBUF. Depending on mode, trampoline into slot-page firmware or translate and
; tail-call Apple Monitor COUT1.
DisplayChar
        LDA $0738,X
        AND #$02
        BEQ LCD26
        LDA $04B8,X
        AND #$38
        BEQ LCD26
        TXA                          ; push $Cn for dynamic slot-page trampoline
        PHA
        LDA #$67                     ; $67 + RTS increment => slot entry $Cn68
        PHA
        RTS
LCD26
        LDA $03B8,X
        ROL A
        ROL A
        ROL A
        AND #$03
        TAY
        LDA CHARBUF
        ORA #$80
        CPY #$01
        BEQ LCD4D
        CMP #$C0
        BCC LCD4D
        CMP #$E0
        BCC LCD47
        EOR #$20
        CPY #$02
        BNE LCD4D
        BEQ LCD4B
LCD47
        CPY #$03
        BNE LCD4D
LCD4B
        AND #$1F
LCD4D
        JMP COUT1                    ; tail-call Apple Monitor output routine
;
; Reconstruct and install Apple's CSW output vector from per-slot saved state.
InstallCsw
        LDX SLOTSAVE
        LDA $0638,X
        STA CSWL
        LDA $04B8,X
        LSR A
        LSR A
        LSR A
        AND #$07
        ORA #$C0
        STA CSWH
        RTS
;
; Save current CSWL and restore CSW/KSW bytes previously stacked.
RestoreVec
        LDA CSWL
        STA $0638,X
        PLA
        STA CSWL
        PLA
        STA CSWH
        PLA
        STA KSWL
        PLA
        STA KSWH
        RTS

; ============================================================================
; SECTION 7 - CONFIGURATION / COMMAND PARSER
; ============================================================================

;
; Configuration/command parser. v2.0 adds lowercase-to-uppercase normalization before dispatching
; command letters.
CfgCommand
        TAY
        LDA CHARBUF
        AND #$7F
        CMP #$20
        BEQ LCDA9
        CMP #$0D
        BNE CfgNonCR
        JSR AltLoad0
        CPY #$04
        BEQ LCD8F
        CPY #$05
        BNE LCDA9
LCD8F
        LDA #$2C
        JSR RtcRead
        JMP CfgAction
CfgNonCR
        CMP #$60                     ; v2.0: fold lowercase command letters to uppercase before parser dispatch
        BCC LCD9D
        AND #$5F
LCD9D
        DEY
        BEQ LCDAA
        DEY
        BEQ LCDD0
        DEY
        BEQ LCDF5
        DEY
        BEQ CfgHotkey
LCDA9
        RTS
LCDAA
        CMP #$20
        BCS LCDBE
        CMP $0538,X
        BNE LCDB9
        DEC $04B8,X
        JMP WaitTx
LCDB9
        STA $0538,X
        BNE AltLoad0
LCDBE
        EOR #$30
        CMP #$0A
        BCS LCDCC
        INC $04B8,X
        LDY #$2B
        JMP LCE85
LCDCC
        LDY #$FD
        BNE CfgLookup
LCDD0
        EOR #$30
        CMP #$0A
        BCS LCDF1
        PHA
        LDA #BR_GFXCTL0
        JSR RtcRead
        ASL A
        TSX
        PHA
        ASL A
        ASL A
        ADC $0100,X
        INX
        ADC $0100,X
        TXS
        LDX SLOTSAVE
        LDY #$2B
        JMP LCE85
LCDF1
        LDY #$3A
        BNE CfgLookup
LCDF5
        LSR A
        EOR #$22
        BNE LCE35
        LDA #BR_GFXCTL1
        JSR RtcRead
        BCC LCE06
        ORA $0738,X
        BNE LCE0B
LCE06
        EOR #$FF
        AND $0738,X
LCE0B
        STA $0738,X
LCE0E
        LDA #$06
        BIT $00A9                    ; bytes $CE11-$CE12 also decode as alternate entry LDA #$00
;
; Replace the low three bits of per-slot state $04B8,X with bits supplied in A.
SetMode
        LDX SLOTSAVE
        EOR $04B8,X
        AND #$07
        EOR $04B8,X
        STA $04B8,X
        RTS
;
; Recognize one of five setup hotkeys and trampoline to slot-page routine $Cn94.
CfgHotkey
        LDY #$04
LCE24
        CMP $CEF2,Y
        BEQ LCE2D
        DEY
        BPL LCE24
        RTS
LCE2D
        LDA SLOTSAVE                 ; push $Cn for dynamic slot-page trampoline to $Cn94
        PHA
        LDA #$93
        PHA
        RTS
LCE35
        LDA #$20
        STA $05B8,X
        JMP LCE0E
;
; Search three-byte command/configuration records in CommandTab.
CfgLookup
        LDA CHARBUF
        AND #$7F
        CMP #$60
        BCC LCE47
        AND #$5F
LCE47
        STA CHARBUF
LCE49
        INY
        INY
        INY
        LDA $CE96,Y
        BEQ LCE35
        EOR CHARBUF
        ASL A
        BNE LCE49
        LDA $CE97,Y
        AND #$20
        BNE LCE64
        LDA $0738,X
        AND #$10
        BNE LCE49
LCE64
        LDA $0738,X
        LSR A
        LSR A
        LDA $CE97,Y
        BCC LCE6F
        ASL A
LCE6F
        BPL LCE49
        LDA $CE97,Y
        JSR SetMode
        LDA $CE97,Y
        AND #$10
        CMP #$10
        LDA $CE98,Y
        BCS CfgAction
        LDY #$2C
LCE85
        PHA                          ; push action and construct slot-page trampoline to $Cn84
        LDA SLOTSAVE
        PHA
        LDA #$83
        PHA
        RTS
;
; Execute a configuration action through the EPROM-bank wrapper.
CfgAction
        TAX
        JSR BankCall                 ; execute configuration/bank action through BankCall
        LDX SLOTSAVE
        RTS
CommandTab
; Three-byte command/configuration records searched by CfgLookup. v2.0 contains four more 3-byte records than v1.4; record semantics remain partly inferred.
        HEX 3FF009      ; key '?'
        HEX 426569
        HEX 438551
        HEX 45E380
        HEX 46E304
        HEX 47A41A
        HEX 489032      ; v2.0 addition vs v1.4: key 'H'
        HEX 499071
        HEX 4B9079
        HEX 4CE301
        HEX 4DE320
        HEX 514561
        HEX 52C559
        HEX 534340
        HEX 539022      ; v2.0 addition vs v1.4: second 'S' record
        HEX 544551
        HEX 548340
        HEX 57902A      ; v2.0 addition vs v1.4: key 'W'
        HEX 58E308
        HEX 5AE589
        HEX 0042F6
        HEX 3943F6
        HEX 1944F6
        HEX 4946F6
        HEX 294890      ; v2.0 changed record (v1.4 was 29 4C F6)
        HEX 3A4CF6      ; v2.0 addition vs v1.4: key ':'
        HEX 214E90
        HEX 8150F6
        HEX 415356
        HEX 3154D6
        HEX 1100        ; table terminator/tail retained verbatim
SetupKeys
; Five configuration hotkeys compared directly by CfgHotkey: ASCII 'SI2MR'.
        HEX 5349324D52
SetupMask
; Five adjacent mask/value bytes associated with the setup hotkeys; exact pairing remains provisional.
        HEX 8040200201

; ============================================================================
; SECTION 8 - POST-CHARACTER DELAY
; ============================================================================

;
; Optional post-character delay for CR/LF/form-feed according to persistent delay configuration.
PostDelay
        ORA #$80
        TAY
        LDA $03B8,X
        CPY #$8C
        BEQ LCF12
        CPY #$8A
        BEQ LCF10
        CPY #$8D
        BNE LCF23
        LSR A
        LSR A
LCF10
        LSR A
        LSR A
LCF12
        AND #$03
        TAY
        LDA $CF24,Y                  ; delay table indexed by selected CR/LF/FF delay mode
        BEQ LCF23
        TAY
LCF1B
        LDA #$08
        JSR DelayLoop
        DEY
        BNE LCF1B
LCF23
        RTS
DelayTab
; Delay-count table: $00,$04,$20,$FA.
        HEX 000420FA
;
; Busy-wait delay primitive. Firmware uses nested counts; timing depends on the Apple II CPU
; clock.
DelayLoop
        PHA
        LDA #$90
LCF2B
        SEC
        SBC #$01
        BNE LCF2B
        PLA
        SBC #$01
        BNE DelayLoop
        RTS

; ============================================================================
; SECTION 9 - UNUSED / ERASED ROM TAIL
; ============================================================================

UnusedFF
; Remaining bytes in this supplied 2 KiB dump are $FF (erased/unprogrammed).
        HEX FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF
        HEX FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF
        HEX FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF
        HEX FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF
        HEX FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF
        HEX FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF
        HEX FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF
        HEX FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF
        HEX FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF
        HEX FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF
        HEX FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF
        HEX FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF
        HEX FFFFFFFFFFFFFFFFFFFF

.END