Property | Value |
Project Name: | c:\xilinx\projects\applefpga |
Target Device: | xc3s200 |
Report Generated: | Friday 11/03/06 at 11:49 |
Printable Summary (View as HTML) | AppleFPGA_summary.html |
Logic Utilization | Used | Available | Utilization | Note(s) |
Total Number Slice Registers: | 782 | 3,840 | 20% | |
Number used as Flip Flops: | 753 | |||
Number used as Latches: | 29 | |||
Number of 4 input LUTs: | 2,815 | 3,840 | 73% | |
Logic Distribution: | ||||
Number of occupied Slices: | 1,763 | 1,920 | 91% | |
Number of Slices containing only related logic: | 1,763 | 1,763 | 100% | |
Number of Slices containing unrelated logic: | 0 | 1,763 | 0% | |
Total Number 4 input LUTs: | 2,996 | 3,840 | 78% | |
Number used as logic: | 2,815 | |||
Number used as a route-thru: | 181 | |||
Number of bonded IOBs: | 116 | 173 | 67% | |
Number of Block RAMs: | 10 | 12 | 83% | |
Number of GCLKs: | 8 | 8 | 100% |
Property | Value |
Number of Unrouted Signals: | All signals are completely routed. |
Number of Failing Constraints: | 0 |
Constraint(s) | Requested | Actual | Logic Levels |
No Constraints Found |
Report Name | Status | Last Date Modified |
Synthesis Report | Current | Friday 11/03/06 at 11:48 |
Translation Report | Current | Friday 11/03/06 at 11:49 |
Map Report | Current | Friday 11/03/06 at 11:49 |
Pad Report | Current | Friday 11/03/06 at 11:49 |
Place and Route Report | Current | Friday 11/03/06 at 11:49 |
Post Place and Route Static Timing Report | Current | Friday 11/03/06 at 11:49 |
Bitgen Report | Current | Friday 11/03/06 at 11:49 |