|MMU
A[0] => mmu_ra:U_MMU_RA.A[0]
A[0] => mmu_md7:U_MMU_MD7.A[0]
A[0] => soft_switches_c05x:U_SOFT_SWITCHES_C05X.D
A[0] => soft_switches_c00x:U_SOFT_SWITCHES_C00X.D
A[0] => mmu_soft_switches_c08x:U_MMU_SOFT_SWITCHES_C08X.A0
A[0] => dev_decoder:U_DEV_DECODER.A[0]
A[0] => mmu_mpon:U_MMU_MPON.A[0]
A[0] => mmu_addr_decoder:U_ADDR_DECODER.A[0]
A[1] => mmu_ra:U_MMU_RA.A[1]
A[1] => mmu_md7:U_MMU_MD7.A[1]
A[1] => soft_switches_c05x:U_SOFT_SWITCHES_C05X.SWITCH_ADDR[0]
A[1] => soft_switches_c00x:U_SOFT_SWITCHES_C00X.SWITCH_ADDR[0]
A[1] => mmu_soft_switches_c08x:U_MMU_SOFT_SWITCHES_C08X.A1
A[1] => dev_decoder:U_DEV_DECODER.A[1]
A[1] => mmu_mpon:U_MMU_MPON.A[1]
A[1] => mmu_addr_decoder:U_ADDR_DECODER.A[1]
A[2] => mmu_ra:U_MMU_RA.A[2]
A[2] => mmu_md7:U_MMU_MD7.A[2]
A[2] => soft_switches_c05x:U_SOFT_SWITCHES_C05X.SWITCH_ADDR[1]
A[2] => soft_switches_c00x:U_SOFT_SWITCHES_C00X.SWITCH_ADDR[1]
A[2] => dev_decoder:U_DEV_DECODER.A[2]
A[2] => mmu_mpon:U_MMU_MPON.A[2]
A[2] => mmu_addr_decoder:U_ADDR_DECODER.A[2]
A[3] => mmu_ra:U_MMU_RA.A[3]
A[3] => mmu_md7:U_MMU_MD7.A[3]
A[3] => soft_switches_c05x:U_SOFT_SWITCHES_C05X.SWITCH_ADDR[2]
A[3] => soft_switches_c00x:U_SOFT_SWITCHES_C00X.SWITCH_ADDR[2]
A[3] => mmu_soft_switches_c08x:U_MMU_SOFT_SWITCHES_C08X.A3
A[3] => dev_decoder:U_DEV_DECODER.A[3]
A[3] => mmu_mpon:U_MMU_MPON.A[3]
A[3] => mmu_addr_decoder:U_ADDR_DECODER.A[3]
A[4] => mmu_ra:U_MMU_RA.A[4]
A[4] => dev_decoder:U_DEV_DECODER.A[4]
A[4] => mmu_mpon:U_MMU_MPON.A[4]
A[4] => mmu_addr_decoder:U_ADDR_DECODER.A[4]
A[5] => mmu_ra:U_MMU_RA.A[5]
A[5] => dev_decoder:U_DEV_DECODER.A[5]
A[5] => mmu_mpon:U_MMU_MPON.A[5]
A[5] => mmu_addr_decoder:U_ADDR_DECODER.A[5]
A[6] => mmu_ra:U_MMU_RA.A[6]
A[6] => dev_decoder:U_DEV_DECODER.A[6]
A[6] => mmu_mpon:U_MMU_MPON.A[6]
A[6] => mmu_addr_decoder:U_ADDR_DECODER.A[6]
A[7] => mmu_ra:U_MMU_RA.A[7]
A[7] => dev_decoder:U_DEV_DECODER.A[7]
A[7] => mmu_mpon:U_MMU_MPON.A[7]
A[7] => mmu_addr_decoder:U_ADDR_DECODER.A[7]
A[8] => mmu_ra:U_MMU_RA.A[8]
A[8] => dev_decoder:U_DEV_DECODER.A[8]
A[8] => mmu_mpon:U_MMU_MPON.A[8]
A[8] => mmu_addr_decoder:U_ADDR_DECODER.A[8]
A[9] => mmu_ra:U_MMU_RA.A[9]
A[9] => dev_decoder:U_DEV_DECODER.A[9]
A[9] => mmu_mpon:U_MMU_MPON.A[9]
A[9] => mmu_addr_decoder:U_ADDR_DECODER.A[9]
A[10] => mmu_ra:U_MMU_RA.A[10]
A[10] => mmu_selmb:U_MMU_SELMB.A10
A[10] => dev_decoder:U_DEV_DECODER.A[10]
A[10] => mmu_mpon:U_MMU_MPON.A[10]
A[10] => mmu_addr_decoder:U_ADDR_DECODER.A[10]
A[11] => mmu_ra:U_MMU_RA.A[11]
A[11] => dev_decoder:U_DEV_DECODER.A[11]
A[11] => mmu_mpon:U_MMU_MPON.A[11]
A[11] => mmu_addr_decoder:U_ADDR_DECODER.A[11]
A[12] => mmu_ra:U_MMU_RA.A[12]
A[12] => dev_decoder:U_DEV_DECODER.A[12]
A[12] => mmu_mpon:U_MMU_MPON.A[12]
A[12] => mmu_addr_decoder:U_ADDR_DECODER.A[12]
A[13] => mmu_ra:U_MMU_RA.A[13]
A[13] => mmu_selmb:U_MMU_SELMB.A13
A[13] => dev_decoder:U_DEV_DECODER.A[13]
A[13] => mmu_mpon:U_MMU_MPON.A[13]
A[13] => mmu_addr_decoder:U_ADDR_DECODER.A[13]
A[14] => mmu_ra:U_MMU_RA.A[14]
A[14] => mmu_selmb:U_MMU_SELMB.A14
A[14] => dev_decoder:U_DEV_DECODER.A[14]
A[14] => mmu_mpon:U_MMU_MPON.A[14]
A[14] => mmu_addr_decoder:U_ADDR_DECODER.A[14]
A[15] => mmu_ra:U_MMU_RA.A[15]
A[15] => mmu_selmb:U_MMU_SELMB.A15
A[15] => dev_decoder:U_DEV_DECODER.A[15]
A[15] => mmu_mpon:U_MMU_MPON.A[15]
A[15] => mmu_addr_decoder:U_ADDR_DECODER.A[15]
PHI_0 => PHI_1.IN0
PHI_0 => mmu_ra:U_MMU_RA.PHI_0
PHI_0 => mmu_en80:U_MMU_EN80.PHI_0
PHI_0 => mmu_md7:U_MMU_MD7.PHI_0
PHI_0 => mmu_romen:U_MMU_ROMEN.PHI_0
PHI_0 => mmu_rw245:U_MMU_RW245.PHI_0
PHI_0 => mmu_casen:UMMU_CASEN.PHI_0
PHI_0 => common_internals:U_COMMON_INTERNALS.PHI_0
PHI_0 => mmu_mpon:U_MMU_MPON.PHI_0
PHI_0 => mmu_addr_decoder:U_ADDR_DECODER.PHI_0
Q3 => mmu_ra:U_MMU_RA.Q3
Q3 => mmu_md7:U_MMU_MD7.Q3
Q3 => common_internals:U_COMMON_INTERNALS.Q3
Q3 => mmu_mpon:U_MMU_MPON.Q3
PRAS_N => mmu_md7:U_MMU_MD7.PRAS_N
PRAS_N => common_internals:U_COMMON_INTERNALS.PRAS_N
PRAS_N => ras_hold_time:U_RAS_HOLD_TIME.PRAS_N
R_W_N => mmu_kbd:U_MMU_KBD.R_W_N
R_W_N => mmu_romen:U_MMU_ROMEN.R_W_N
R_W_N => mmu_rw245:U_MMU_RW245.R_W_N
R_W_N => mmu_casen:UMMU_CASEN.R_W_N
R_W_N => mmu_selmb:U_MMU_SELMB.R_W_N
R_W_N => common_internals:U_COMMON_INTERNALS.R_W_N
R_W_N => soft_switches_c00x:U_SOFT_SWITCHES_C00X.R_W_N
R_W_N => mmu_soft_switches_c08x:U_MMU_SOFT_SWITCHES_C08X.R_W_N
INH_N => INH.IN0
INH_N => mmu_en80:U_MMU_EN80.INH_N
INH_N => mmu_rw245:U_MMU_RW245.INH_N
DMA_N => mmu_rw245:U_MMU_RW245.DMA_N
ORA[0] <= i~11
ORA[1] <= i~10
ORA[2] <= i~9
ORA[3] <= i~8
ORA[4] <= i~7
ORA[5] <= i~6
ORA[6] <= i~5
ORA[7] <= i~4
EN80_N <= mmu_en80:U_MMU_EN80.EN80_N
KBD_N <= mmu_kbd:U_MMU_KBD.KBD_N
ROMEN1_N <= mmu_romen:U_MMU_ROMEN.ROMEN1_N
ROMEN2_N <= mmu_romen:U_MMU_ROMEN.ROMEN2_N
MD7 <= i~2
R_W_N_245 <= mmu_rw245:U_MMU_RW245.R_W_N_245
CASEN_N <= mmu_casen:UMMU_CASEN.CASEN_N
CXXXOUT <= i~0


|MMU|ras_hold_time:U_RAS_HOLD_TIME
PRAS_N => INITIAL_DELAY.DATAIN
RAS_N <= g_GENERATE_DELAY_12_DELAY


|MMU|mmu_addr_decoder:U_ADDR_DECODER
A[0] => i~33.IN0
A[1] => i~32.IN0
A[2] => i~31.IN0
A[3] => i~30.IN0
A[4] => i~29.IN0
A[4] => ls138:MMU_1_J5.A
A[5] => i~28.IN0
A[5] => ls138:MMU_1_J5.B
A[6] => i~27.IN0
A[6] => ls138:MMU_1_J5.C
A[7] => i~26.IN0
A[7] => ls138:MMU_1_J5.G2A_N
A[8] => i~15.IN0
A[8] => i~18.IN0
A[8] => i~25.IN0
A[9] => i~14.IN1
A[9] => i~16.IN0
A[9] => i~24.IN0
A[9] => i~39.IN1
A[10] => i~14.IN0
A[10] => i~17.IN0
A[10] => i~23.IN0
A[10] => i~39.IN0
A[11] => C8_FXX_INT.IN0
A[11] => i~8.IN0
A[11] => i~13.IN0
A[11] => i~38.IN0
A[12] => i~1.IN0
A[12] => i~2.IN0
A[12] => i~6.IN0
A[12] => i~37.IN0
A[13] => i~0.IN0
A[13] => i~4.IN0
A[13] => i~36.IN0
A[14] => CXXX_FXXX_INT.IN1
A[14] => i~35.IN1
A[15] => CXXX_FXXX_INT.IN0
A[15] => i~35.IN0
PHI_0 => i~22.IN0
CXXX_FXXX <= CXXX_FXXX_INT
FXXX_N <= FXXX_N_INT
EXXX_N <= EXXX_N_INT
DXXX_N <= DXXX_N_INT
CXXX <= CXXX_INT
C8_FXX <= C8_FXX_INT
C8_FXX_N <= i~7
C0_7XX_N <= i~10
E_FXXX_N <= E_FXXX_N_INT
D_FXXX <= i~11
MC0XX_N <= MC0XX_N_INT
MC3XX <= i~21
MC00X_N <= ls138:MMU_1_J5.Y0
MC01X_N <= ls138:MMU_1_J5.Y1
MC04X_N <= ls138:MMU_1_J5.Y4
MC05X_N <= ls138:MMU_1_J5.Y5
MC06X_N <= ls138:MMU_1_J5.Y6
MC07X_N <= ls138:MMU_1_J5.Y7
MCFFF_N <= i~34
PHI_0_7XX <= PHI_0_7XX_INT
PHI_0_1XX_N <= PHI_0_1XX_N_INT
S_01XX_N <= i~40


|MMU|mmu_addr_decoder:U_ADDR_DECODER|ls138:MMU_1_J5
A => NOT_A.IN0
A => i~3.IN0
A => i~8.IN0
A => i~13.IN0
A => i~18.IN0
B => NOT_B.IN0
B => i~2.IN0
B => i~12.IN0
C => NOT_C.IN0
C => i~2.IN1
C => i~7.IN0
G1 => i~0.IN0
G2A_N => i~1.IN0
G2B_N => G_N.IN0
Y0 <= i~4
Y1 <= i~6
Y2 <= i~9
Y3 <= i~11
Y4 <= i~14
Y5 <= i~16
Y6 <= i~19
Y7 <= i~21


|MMU|mmu_mpon:U_MMU_MPON
A[0] => reduce_nor_17.IN1
A[1] => reduce_nor_17.IN0
A[2] => i~0.IN0
A[3] => i~1.IN0
A[4] => i~2.IN0
A[5] => i~3.IN0
A[6] => i~4.IN0
A[7] => i~5.IN0
A[8] => i~6.IN0
A[9] => i~7.IN0
A[10] => i~8.IN0
A[11] => i~9.IN0
A[12] => i~10.IN0
A[13] => i~11.IN0
A[14] => i~12.IN0
A[15] => i~13.IN0
S_01XX_N => M5_2.DATAIN
PHI_0 => M5_7.CLK
PHI_0 => DELTA_01XX_N.CLK
PHI_0 => i~14.IN0
PHI_0 => M5_2.CLK
Q3 => i~14.IN1
MPON_N <= i~16


|MMU|dev_decoder:U_DEV_DECODER
A[4] => ls138:MMU_1_P3.A
A[5] => ls138:MMU_1_P3.B
A[6] => ls138:MMU_1_P3.C
A[7] => ls138:MMU_1_P3.G1
PHI_1 => ls138:MMU_1_P3.G2B_N
MC0XX_N => ls138:MMU_1_P3.G2A_N
DEV0_N <= ls138:MMU_1_P3.Y0
DEV1_N <= ls138:MMU_1_P3.Y1
DEV2_N <= ls138:MMU_1_P3.Y2
DEV5_N <= ls138:MMU_1_P3.Y5
DEV6_N <= ls138:MMU_1_P3.Y6


|MMU|dev_decoder:U_DEV_DECODER|ls138:MMU_1_P3
A => NOT_A.IN0
A => i~3.IN0
A => i~8.IN0
A => i~13.IN0
A => i~18.IN0
B => NOT_B.IN0
B => i~2.IN0
B => i~12.IN0
C => NOT_C.IN0
C => i~2.IN1
C => i~7.IN0
G1 => i~0.IN0
G2A_N => i~1.IN0
G2B_N => G_N.IN0
Y0 <= i~4
Y1 <= i~6
Y2 <= i~9
Y3 <= i~11
Y4 <= i~14
Y5 <= i~16
Y6 <= i~19
Y7 <= i~21


|MMU|mmu_soft_switches_c08x:U_MMU_SOFT_SWITCHES_C08X
MPON_N => i~3.IN0
A0 => i~0.IN0
A0 => D3.IN0
A0 => D4.IN0
A1 => i~0.IN1
A3 => i~4.IN0
A3 => BANK1~reg0.DATAIN
DEV0_N => CLK.IN0
R_W_N => D3.IN1
IN_FST_ACC => i~1.IN0
IN_WREN => i~2.IN0
BANK1 <= BANK1~reg0
BANK2 <= BANK2~reg0
RDRAM <= RDRAM~reg0
RDROM <= RDROM~reg0
OUT_FST_ACC <= OUT_FST_ACC~reg0
WRPROT <= WRPROT~reg0
OUT_WREN <= OUT_WREN~reg0


|MMU|soft_switches_c00x:U_SOFT_SWITCHES_C00X
D => latch_9334:SOFT_SWITCHES_LATCH.D
SWITCH_ADDR[0] => latch_9334:SOFT_SWITCHES_LATCH.ADDR[0]
SWITCH_ADDR[1] => latch_9334:SOFT_SWITCHES_LATCH.ADDR[1]
SWITCH_ADDR[2] => latch_9334:SOFT_SWITCHES_LATCH.ADDR[2]
C00X_N => i~0.IN0
R_W_N => i~0.IN1
RESET_N => latch_9334:SOFT_SWITCHES_LATCH.C_N
PHI_1 => ENABLE_N.IN0
EN80VID <= latch_9334:SOFT_SWITCHES_LATCH.Q0
FLG1 <= latch_9334:SOFT_SWITCHES_LATCH.Q1
FLG2 <= latch_9334:SOFT_SWITCHES_LATCH.Q2
PENIO_N <= latch_9334:SOFT_SWITCHES_LATCH.Q3
ALTSTKZP <= latch_9334:SOFT_SWITCHES_LATCH.Q4
INTC300_N <= latch_9334:SOFT_SWITCHES_LATCH.Q5
INTC300 <= i~1
S_80COL <= latch_9334:SOFT_SWITCHES_LATCH.Q6
PAYMAR <= latch_9334:SOFT_SWITCHES_LATCH.Q7


|MMU|soft_switches_c00x:U_SOFT_SWITCHES_C00X|latch_9334:SOFT_SWITCHES_LATCH
C_N => i~1.IN0
C_N => i~3.IN0
C_N => i~5.IN0
C_N => i~7.IN0
C_N => i~9.IN0
C_N => i~11.IN0
C_N => i~13.IN0
C_N => i~15.IN0
E_N => i~0.OUTPUTSELECT
E_N => i~2.OUTPUTSELECT
E_N => i~4.OUTPUTSELECT
E_N => i~6.OUTPUTSELECT
E_N => i~8.OUTPUTSELECT
E_N => i~10.OUTPUTSELECT
E_N => i~12.OUTPUTSELECT
E_N => i~14.OUTPUTSELECT
D => Mux_5.IN0
D => Mux_6.IN0
D => Mux_7.IN0
D => Mux_8.IN0
D => Mux_9.IN0
D => Mux_10.IN0
D => Mux_11.IN0
D => Mux_12.IN0
ADDR[0] => Mux_5.IN3
ADDR[0] => Mux_6.IN3
ADDR[0] => Mux_7.IN3
ADDR[0] => Mux_8.IN3
ADDR[0] => Mux_9.IN3
ADDR[0] => Mux_10.IN3
ADDR[0] => Mux_11.IN3
ADDR[0] => Mux_12.IN3
ADDR[1] => Mux_5.IN2
ADDR[1] => Mux_6.IN2
ADDR[1] => Mux_7.IN2
ADDR[1] => Mux_8.IN2
ADDR[1] => Mux_9.IN2
ADDR[1] => Mux_10.IN2
ADDR[1] => Mux_11.IN2
ADDR[1] => Mux_12.IN2
ADDR[2] => Mux_5.IN1
ADDR[2] => Mux_6.IN1
ADDR[2] => Mux_7.IN1
ADDR[2] => Mux_8.IN1
ADDR[2] => Mux_9.IN1
ADDR[2] => Mux_10.IN1
ADDR[2] => Mux_11.IN1
ADDR[2] => Mux_12.IN1
Q0 <= i~1
Q1 <= i~3
Q2 <= i~5
Q3 <= i~7
Q4 <= i~9
Q5 <= i~11
Q6 <= i~13
Q7 <= i~15


|MMU|soft_switches_c05x:U_SOFT_SWITCHES_C05X
D => Mux_5.IN0
D => Mux_6.IN0
D => Mux_7.IN0
D => Mux_8.IN0
D => Mux_9.IN0
D => Mux_10.IN0
D => Mux_11.IN0
D => Mux_12.IN0
SWITCH_ADDR[0] => Mux_5.IN3
SWITCH_ADDR[0] => Mux_6.IN3
SWITCH_ADDR[0] => Mux_7.IN3
SWITCH_ADDR[0] => Mux_8.IN3
SWITCH_ADDR[0] => Mux_9.IN3
SWITCH_ADDR[0] => Mux_10.IN3
SWITCH_ADDR[0] => Mux_11.IN3
SWITCH_ADDR[0] => Mux_12.IN3
SWITCH_ADDR[1] => Mux_5.IN2
SWITCH_ADDR[1] => Mux_6.IN2
SWITCH_ADDR[1] => Mux_7.IN2
SWITCH_ADDR[1] => Mux_8.IN2
SWITCH_ADDR[1] => Mux_9.IN2
SWITCH_ADDR[1] => Mux_10.IN2
SWITCH_ADDR[1] => Mux_11.IN2
SWITCH_ADDR[1] => Mux_12.IN2
SWITCH_ADDR[2] => Mux_5.IN1
SWITCH_ADDR[2] => Mux_6.IN1
SWITCH_ADDR[2] => Mux_7.IN1
SWITCH_ADDR[2] => Mux_8.IN1
SWITCH_ADDR[2] => Mux_9.IN1
SWITCH_ADDR[2] => Mux_10.IN1
SWITCH_ADDR[2] => Mux_11.IN1
SWITCH_ADDR[2] => Mux_12.IN1
C05X_N => i~0.OUTPUTSELECT
C05X_N => i~2.OUTPUTSELECT
C05X_N => i~4.OUTPUTSELECT
C05X_N => i~6.OUTPUTSELECT
C05X_N => i~8.OUTPUTSELECT
C05X_N => i~10.OUTPUTSELECT
C05X_N => i~12.OUTPUTSELECT
C05X_N => i~14.OUTPUTSELECT
RESET_N => i~1.IN0
RESET_N => i~3.IN0
RESET_N => i~5.IN0
RESET_N => i~7.IN0
RESET_N => i~9.IN0
RESET_N => i~11.IN0
RESET_N => i~13.OUTPUTSELECT
RESET_N => i~15.OUTPUTSELECT
ITEXT <= i~13
MIX <= i~15
PG2 <= i~1
HIRES <= i~3
AN0 <= i~5
AN1 <= i~7
AN2 <= i~9
AN3 <= i~11


|MMU|common_internals:U_COMMON_INTERNALS
R_W_N => i~0.IN0
C01X_N => i~1.IN0
PRAS_N => Q3_PRAS_N_INT.IN0
Q3 => Q3_PRAS_N_INT.IN1
PHI_0 => i~2.IN0
PHI_0 => i~4.DATAA
RC01X_N <= i~1
P_PHI_0 <= i~3
P_PHI_1 <= i~4
Q3_PRAS_N <= Q3_PRAS_N_INT


|MMU|mmu_selmb:U_MMU_SELMB
A15 => i~0.IN0
A14 => i~0.IN1
A13 => i~1.IN0
A10 => i~3.IN0
HIRES => i~2.IN0
PHI_0_7XX => i~3.IN1
EN80VID => L2_11.IN0
PG2 => i~10.IN0
FLG1 => i~5.IN0
FLG2 => i~7.IN0
R_W_N => i~5.IN1
R_W_N => i~6.IN0
ALTSTKZP => L3_4.IN0
D_FXXX => i~11.IN0
PHI_0_1XX_N => S3_3.IN0
SELMB_N <= i~12


|MMU|mmu_casen:UMMU_CASEN
RDROM => i~0.IN0
CXXX => PCASEN_N_INT.IN0
D_FXXX => i~0.IN1
D_FXXX => i~2.IN0
R_W_N => i~1.IN0
R_W_N => i~3.IN0
WRPROT => i~2.IN1
INH => i~7.IN0
SELMB_N => i~6.IN0
MPON_N => i~8.IN0
PCASEN_N <= PCASEN_N_INT
OCASEN_N <= i~9
CASEN_N <= i~9


|MMU|mmu_internals:UMMU_INTERNALS
C8_FXX => i~2.IN0
MCFFF_N => RSTC8_N.IN0
PHI_1 => L5_6.IN0
INTC300 => INTC3ACC_N_INT.IN0
MC00X_N => i~4.IN0
MC01X_N => i~4.IN1
MC3XX => INTC3ACC_N_INT.IN1
MPON_N => RSTC8_N.IN1
PENIO_N => i~3.IN0
MC0XX_N => i~3.IN1
INTC8EN <= INTC8EN_INT
INTC8ACC <= i~2
INTC3ACC_N <= INTC3ACC_N_INT
CENROM1 <= i~3
INTIO_N <= i~4


|MMU|mmu_cxxxout:U_MMU_CXXXOUT
CENROM1 => i~0.IN0
INTC8ACC => i~2.IN0
INTC3ACC_N => i~1.IN0
CXXX => i~3.IN0
CXXXOUT_N <= i~4


|MMU|mmu_rw245:U_MMU_RW245
INTIO_N => i~0.IN0
CXXXOUT_N => P7_8.IN0
R_W_N => P9_11.IN0
R_W_N => i~1.IN0
R_W_N => E2_11.IN0
DMA_N => DMA.IN0
DMA_N => L4_3.IN0
INH_N => PRW245.OUTPUTSELECT
PHI_0 => i~2.IN0
R_W_N_245 <= i~2


|MMU|mmu_romen:U_MMU_ROMEN
PHI_0 => i~1.IN0
PHI_0 => i~5.IN0
PHI_0 => D2_12.IN0
INTC8ACC => i~7.IN0
INTC3ACC_N => i~6.IN0
CXXX => i~4.IN0
DXXX_N => L5_11.IN0
E_FXXX_N => i~2.IN0
INH => i~3.IN0
INH => i~10.IN0
RDROM => i~0.IN0
CENROM1 => i~4.IN1
R_W_N => i~0.IN1
ROMEN2_N <= i~3
ROMEN1_N <= i~10


|MMU|mmu_md7:U_MMU_MD7
RC01X_N => i~1.IN0
A[0] => i~4.IN1
A[0] => i~11.IN0
A[0] => Mux_23.IN11
A[1] => i~2.IN1
A[1] => i~9.IN0
A[1] => Mux_23.IN10
A[2] => i~0.IN1
A[2] => i~7.IN0
A[2] => Mux_23.IN9
A[3] => i~0.IN0
A[3] => i~2.IN0
A[3] => i~4.IN0
A[3] => i~6.IN0
A[3] => Mux_23.IN8
PHI_0 => i~13.IN0
PHI_0 => i~16.IN0
Q3 => i~14.IN0
PRAS_N => i~15.IN0
BANK2 => Mux_23.IN12
RDRAM => Mux_23.IN13
FLG1 => Mux_23.IN14
FLG2 => Mux_23.IN15
PENIO_N => Mux_23.IN16
ALTSTKZP => Mux_23.IN17
INTC300_N => Mux_23.IN18
EN80VID => Mux_23.IN19
ENABLE_N <= i~18


|MMU|mmu_en80:U_MMU_EN80
SELMB_N => i~0.IN0
INH_N => i~2.IN0
PHI_0 => i~3.IN0
PCASEN_N => i~1.IN0
EN80_N <= i~3


|MMU|mmu_kbd:U_MMU_KBD
INTIO_N => i~1.IN0
R_W_N => i~0.IN0
PHI_1 => i~2.IN0
KBD_N <= i~2


|MMU|mmu_ra:U_MMU_RA
A[0] => ra_mux:IOU_RA_MUX.ROW_RA0
A[1] => ra_mux:IOU_RA_MUX.ROW_RA1
A[2] => ra_mux:IOU_RA_MUX.ROW_RA2
A[3] => ra_mux:IOU_RA_MUX.ROW_RA3
A[4] => ra_mux:IOU_RA_MUX.ROW_RA4
A[5] => ra_mux:IOU_RA_MUX.ROW_RA5
A[6] => ra_mux:IOU_RA_MUX.COL_RA1
A[7] => ra_mux:IOU_RA_MUX.ROW_RA6
A[8] => ra_mux:IOU_RA_MUX.ROW_RA7
A[9] => ra_mux:IOU_RA_MUX.COL_RA0
A[10] => ra_mux:IOU_RA_MUX.COL_RA2
A[11] => ra_mux:IOU_RA_MUX.COL_RA3
A[12] => MA12.IN0
A[13] => ra_mux:IOU_RA_MUX.COL_RA5
A[14] => ra_mux:IOU_RA_MUX.COL_RA6
A[15] => ra_mux:IOU_RA_MUX.COL_RA7
RAS_N => ra_mux:IOU_RA_MUX.RAS_N
PHI_0 => ra_mux:IOU_RA_MUX.PHI
Q3 => ra_mux:IOU_RA_MUX.Q3
DXXX_N => i~0.IN0
BANK1 => i~1.IN0
RA[0] <= ra_mux:IOU_RA_MUX.RA0
RA[1] <= ra_mux:IOU_RA_MUX.RA1
RA[2] <= ra_mux:IOU_RA_MUX.RA2
RA[3] <= ra_mux:IOU_RA_MUX.RA3
RA[4] <= ra_mux:IOU_RA_MUX.RA4
RA[5] <= ra_mux:IOU_RA_MUX.RA5
RA[6] <= ra_mux:IOU_RA_MUX.RA6
RA[7] <= ra_mux:IOU_RA_MUX.RA7
RA_ENABLE_N <= ra_mux:IOU_RA_MUX.RA_ENABLE_N


|MMU|mmu_ra:U_MMU_RA|ra_mux:IOU_RA_MUX
PHI => i~0.IN0
PHI => i~1.IN0
RAS_N => i~4.IN0
RAS_N => i~7.OUTPUTSELECT
RAS_N => i~8.OUTPUTSELECT
RAS_N => i~9.OUTPUTSELECT
RAS_N => i~10.OUTPUTSELECT
RAS_N => i~11.OUTPUTSELECT
RAS_N => i~12.OUTPUTSELECT
RAS_N => i~13.OUTPUTSELECT
RAS_N => i~14.OUTPUTSELECT
Q3 => i~0.IN1
Q3 => i~2.IN0
ROW_RA0 => i~7.DATAB
ROW_RA1 => i~8.DATAB
ROW_RA2 => i~9.DATAB
ROW_RA3 => i~10.DATAB
ROW_RA4 => i~11.DATAB
ROW_RA5 => i~12.DATAB
ROW_RA6 => i~13.DATAB
ROW_RA7 => i~14.DATAB
COL_RA0 => i~7.DATAA
COL_RA1 => i~8.DATAA
COL_RA2 => i~9.DATAA
COL_RA3 => i~10.DATAA
COL_RA4 => i~11.DATAA
COL_RA5 => i~12.DATAA
COL_RA6 => i~13.DATAA
COL_RA7 => i~14.DATAA
RA_ENABLE_N <= i~6
RA0 <= i~7
RA1 <= i~8
RA2 <= i~9
RA3 <= i~10
RA4 <= i~11
RA5 <= i~12
RA6 <= i~13
RA7 <= i~14


