Frozen Signal's IOU and MMU replacement adapters.

I am starting this thread so I can ask for some feedback on my designs for an adapter for the IOU and MMU. As I mentionned in this thread:  https://www.applefritter.com/comment/110444#comment-110444, ReActiveMicro originally offered to design the hardware for the replacement adapters. However, Henry told me recently that he wouldn't be able to work on this any time soon given his lack of free time. So, I decided to revisit an attempt I did some time ago.

The VHDL code for my project (https://github.com/frozen-signal/Apple_IIe_MMU_IOU) was developped using an ALTERA EPM7128STC. But, this CPLD is not produced anymore and the only way to buy them is to find them on places like eBay and AliExpress. The CPLDs that comes from these places are unlikely to be new ones; they are probably pulls or recycled ones in some way. So, each chip must be tested indivually to make sure it works. A tedious task. Besides, the irony of using obsolete CPLDs to replace obsolete ASICs don't escape me.

So, designing the replacement adapters with modern and active compnents makes sense. This is what is needed:

 - A FPGA with at least 38 GPIOs and small enough to fit on PCB the size of a 40-pin DIP.

 - Ideally, the FPGA should have an internal oscillator to generate some hold delays that the Apple IIe requires.

 - All the components must be active, inexpensive and easy to source.

 - The PCB must only require basic PCB manufacturing and be relatively easy to assemble for a hobbyist.

The Lattice iCE40 FPGA (ICE5LP1K-SG48ITR) fits that bill; a 7x7 mm, QFN-48 package that is very popular with the hobbyists and has an internal 48 MHz oscillator.

FPGA.png

On the downside it's a 1.2V device with 3.3V banks, so every inputs and bidirectional signals need to be voltage level shifted down to 3.3V. The main challenge is to fit all the level translation onto a PCB the size the official IOU and MMU.

Also, although it has enough GPIOs, 4 of them are shared with the configuration pins. For those unfamiliar, this means that when the iCE40 is powered on, it uses 4 special pins SPI to read its configuration data from a Flash Memory IC. Once the configuration is done, these 4 pins becomes available as GPIO.

Note the KSTRB and AKD signals that are shared with FPGA_SCK and FPGA_SI respectively, more on this later.

U1.png

For the bidirectional signals ORA6-0, a LSF0108 is used for level-translation. This device don't need a direction pin which is really good, but need a bias resistor (R9) and a pull-up for each channel on the high-voltage side (see table 9-3 of  https://www.ti.com/lit/ds/symlink/lsf0108.pdf  to understand where the value of 581 Ohms comes from). /PRAS is an input-only signal but is routed through this component because a channel was free. This is why R7 is DNP; the pull-up is optional for an input signal, but the footprint will be there if needed. 

U5.png

The LVC245 level-shift input-only signals and would be pretty straightforward if it was not for KSTRB and AKD. These two signals are shared with the FPGA SPI pins and we must make sure that external KSTRB or AKD signals don't mess with the SPI signals during the FPGA's configuration. The way to do it is to disable the LVC245 with /OE during configuration time.

I use CDONE, this signal is LOW during configuration and driven HIGH in user mode. Unfortunately, that's the inverse of what we need, we'll have to invert CDONE:

Q2.png

Here, when CDONE is LOW, the NMOS will be in a non-conducting state, and /OE_245 will be pulled-up by R14. When the configuration has finished CDONE will be driven HIGH and the NMOS will turn on driving /OE_245 LOW.

I could also do it with a GPIO:

  - Move an input pin to FPGA_SO (FPGA_SS can't be used because the Flash Mem need to remain unselected in user mode)

  - Pull-up that freed GPIO. During configuration, all GPIOs are placed in a high-impedance state.

  - Configure that GPIO as open-drain and drive it a constant LOW in user mode.

I just preferred to use the FPGA's CDONE signal with an NMOS.

I use the DMG1012TQ-7 because it's small, it's logic-level (VGS(th) = ~0.75V) and has low RDS(on). Plus, it's inexpensive and places like Mouser have these in large quantities.

The /RESET signal also need special handling:

U3.png

In the official IOU, this signal is an open-drain pin with an internal pull-up. To level-shift these with a LSF010x, a pull-up is required on both sides. And since GPIOs are in a high-impedance state during configuration, that means /RESET will be pulled HIGH during this time, and this is not what we want. The fix is simple, fortunately: CDONE is itself an open-drain with weak pull-up, and shorting CDONE with /RESET will give us the desired behaviour.

The remainder of the schematic is standard stuff:

FLASH.png

 - A Winbond W25X20CLUXIG Flash Memory: a SPI Flash module that is small, inexpensive and in ample supply. Note that CLK and DO are tied to KSTRB and AKD respectively. During configuration, KSTRB and AKD won't mess with the SPI signals because as seen earlier, the LVC245 will stop outside's KSTRB and AKD from messing the data. And once the configuration is done, /CS will be held HIGH and CLK and DO signals from outside will be ignored.

LDOs.png

 - MIC5504-3.3YM5 and MIC5365-1.2YC5 LDOs are used to convert 5V to 3.3V and 1.2V. I used these because, like the other components, they are small, inexpensive, easy to solder and easy to source.

There are two problems with the current design: CASSO and SPKR are tied directly to the adapter's pin and are 3.3V. Since these two aren't used as logic signals, I may have to level-shift them to 5V. SPKR is amplified and may be okay, but CASSO probably won't be.

Assembling:

Front_IOU.png

Back_IOU.png

I moved components to the front side as much as I could, and only resistors and capacitors remains on the back. So, the easiest way to assemble the adapter would be reflow the back first. Then, only light 0402 components will be on the underside during the second reflow cycle, minimizing solder joint sagging. With a hot plate & hot air, I think the best way will be to reflow the front, and then solder the back with hot air.

Finally, just like the VHDL part of this project, I plan to upload the Kicad schematics on github once I know they works. I will use the same license (Creative Commons Zero) so that anyone can use them in any way they want. And as a sort-of disclaimer, I have no intention of making money from this project, and I have no problem if other people makes money from this project.

As always, any thoughts are very welcome.