Close but no cigar

Even a near miss is still a miss. I have not gotten the system to boot. I have all the Apple ][+ memory map finished. I also added some of the 2e stuff. I am having problems with the LPC ROM, of course. Debug is going slowly. In the process of looking at the memory map, I noticed a few things that I had forgotten. My original plan was to use RAM for all the ROMs. When I was looking at some of the aspects of the Language Card, I noticed the 4k block that needed to be relocated from C000 to D000. It is weird that I do not remember that feature from my old Apple hardware. Well, I guess it has been 15 years since I did anything with it. With the flat memory map that the CPLD, it is harder to relocate this memory. I could burn a whole 64k of memory for this additional 4k, but I won't. So I have made the modification to use the CPLD internal memory for the 12k of normal ROM and the upper 16k of RAM as the Language Card. The external memory is 32 bits wide. I plan on using the forst 8 bits as the main RAM / Language card RAM. The second 8 bits will be the Auxillary 64k of the 2e. The remaining 16 bits will be used as a 512k RAM card. I have not done any research on how this works, so I am not sure what form it will take.

I took another look at the CPLD utilization. It is not as high as I thought. I am not sure how they calculate the utilization, but the logic is actually low. Even though I am seeing 70% utilization, the logic cells are about 50% and the used latches are at 20%. The internal memory is at 100%, so I assume this plays an important part in the report. This means that I have not removed the OSI functionality. I plan on supporting some type of real time clock. Since I already have the clock being displayed on the bottom of the screen, I want to use one slot as the interface to the clock. So far, I am planning on using these slots for these functions.

1 Serial port
4 512k Memory
5 LPC Flash interface
6 Floppy emulation
7 IDE / CF PRODOS bootable