a quick&dirty mini-project.
Some of you have built an Apple-1 case, but in some cases it may not have enough vertical space to accommodate "some" cards.
To overcome this problem, I have designed a small Riser Card that allows you to house them horizontally, above the RAM (which doesn't heat up, anyway).
Of course, this is especially for those of you who have built a nontransparent case... ;-)
The total height footprint of the Riser+Card should be less or equal to the ACI alone (~40mm above the top side of the EDGE connector).
I also included the six termination resistors suggested by UncleBernie, which remain optional. I am running some tests without them and so far I have had no problems.
(@UncleBernie let me know if this is ok for you.)
There are two PCBs versions available: with and without the mounting holes for the EDGE connector.
You can find the whole project freely downloadable and reproducible here:
Claudio - P-LAB
It is like you can read my mind, this will come in very useful! Thank you as always for sharing your projects in this fashion.
I'm in the process of building a case for my Apple-1 build right now. I'm making it tall enough that it should be able to accommodate most cards, but this could still come in handy. It's a bit smaller than the 2 slot riser that was posted here before. This one would be better to use when only one card is needed.
In post #1, p_lab wrote:
"I also included the six termination resistors suggested by UncleBernie, which remain optional. I am running some tests without them and so far I have had no problems. (@UncleBernie let me know if this is ok for you.)"
Uncle Bernie comments:
I have no copyright on these six damping resistors nor did I apply for a patent for that. Anyone is welcome to use any of the stuff I have published on Applefritter. So it's OK for me if you add or leave out these damping resistors. I'd think it is indeed beneficial if you provide solder pads for them. So anyone using your riser card can add them as needed. According to my experience with ~100 Apple-1 kits it depends very much on the type and the manufacturer of the DRAMs if they are happy in an Apple-1 without my "reliability mods" or if they puke. The Motorola MCM4027 which I had in the beginning needed all the "reliability mods" as published here on Applefritter in an earlier thread. Mostek MK4027 which I had for a while after that were less sensitive and typically only needed the six damping resistors. After the Mostek ones ran out I had the Intersil MK4027 in CERDIP packages which have been in the kits since a year or so and Armin also uses them for his "wave soldered Apple-1" project --- which as we all know was an old project of mine which lead to my (stupid) purchase of allmost all the ICs for 100 Apple-1 even before I had built one. Armin was able to pick up the ball I had to drop due to the fallout of the pandemic on the American electronics industry, especially all the smaller shops who had to close down. And, it was him who enabled me to get at these Intersil MK4027 for a good price. Actually I just jumped onto his huuuuge purchase of those DRAMs. And we were lucky to find out that these Intersil MK4027 DRAMs not only had 1970's date codes but thay also turned out to be the most robust DRAMs for the Apple-1 I have ever encountered. So Armin was able to chose to not put any "reliability mods" into his wave soldered, industrially "mass" produced Apple-1, for best authentic looks, and they still work fine. But don't forget that the high performance bypass capacitors we have selected for his production runs also contribute to better robustness, too. Some of the builders of my kits with the Intersils have provided feedback that they did not need any "reliability mods" either. Since then I have modified my "Tips & Tricks" pdf for builders of my kits to make soldering in the damping resistors and the extra bypass capacitors comprising the "reliability mods" optional. The diagnostics page in my PROMs which come with the kits will tell, and if memory errors do occur, add the six damping resistors first. It seems that is enough. Never heard that those Intersil DRAM needed extra bypass capacitors. Keep in mind however, that the bypass capacitors in my kits have been modern high performance types, too, despite they are still "vintage" looking discs.
Oh man - how many words for this simple topic. But getting to where we are now has been a tedious learning process over three long years. I wrote about that "cliff of unreliability" several times. The Apple-1 in its original form was too close to this cliff but more often than not it worked OK. Some specimen, not so much. Lisa Loop's machine an example, crashing too often. As the story goes (see Tom Owad's "Back to the Garage" ebook), Woz himself tried to fix this example but he could only inprove it so much.
Now, if you have an Apple-1 clone which works robustly, and if you plug in any riser or extension card that lengthens the multiplexed address bus lines even more, then you move the machine closer to the cliff again, possibly undoing all the progress we have made in the past three years.
But you could add D-Latches for all address lines on this riser card, even vintage looking DIL packages such as the 74373 would fit nicely near the edge connector. The latch enable input G could be driven with a delayed version of the fake PHI1 on the bus. A delay of ~100ns could be made with a simple RC - no issue as that input has a Schmitt Trigger. The designers of the SN74373 obviously were clever to make the part more useful.
Adding these D-Latches would have the benefit to fix the address hold time issues and the ringing issues on the address lines downstream of these latches once and for all. The downside is that any downstream cards could not generate their own DMA addresses anymore - these would not reach the address lines on the motherboard. A fight against the D-Latches could be avoided by gating their tristate drivers with the DMA signal but to restore the DMA capability you woud need to add tristate drivers in the back direction. I don't know any card for the Apple-1 using DMA, though.
Note that this suggestion on how to wire in the D-Latches is from memory and should be verified against the datasheets. The idea is that the latch opens one RC delay after the PHI1 phase has started, passes the address through when it stabilizes, and then closes the latch gate once RC delay after the begin of PHI2, so it will keep the address stable until well into the next PHI1.
This trick has been helpful to mitigate some of the bus timing problems you will run into if you try to hook modern, fast SRAMs to any 6502 while still using TTL derived control signals. This means that the 6502 bus timing design is fundamentally flawed, and if you look at the transistor level schematic of the 6502 it gets worse. Actually, the foul trick Woz uses (making his own 'fake' PHI1 and PHI2 signals while ignoring those offered by the 6502 on its pins #3 and #39) helps to mitigate this problem and otherwise none of the Apple-1 daughter cards using fast modern SRAMs would work, unless they would make their own SRAM control signal timing while looking into the future - which is not possible without a faster clock locally generated.
This problem with the botched 6502 bus timing concept shown in all application notes to use PHI2 to gate data transfers has plagued 6502 based microcomputers since the mid 1980s, when SRAMs became fast enough to notice the crumbling addresses from the 6502 at the end of each CPU cycle. Even one of my own products of back in the day was affected and had to be redesigned with a local clock generator and timing sequencer.
Note that this criticism of mine on the 6502 does not imply its designers were idots. No, they were competent digital IC designers. I think they just did not anticipate that somebody would still use their slow NMOS 6502 based on a 7 um process technology (after the optical mask shrink, early 6502 had, IIRC, 8 um channel length) more than a decade (!) after it hit the market. From the early 1980s on everybody else started to use polysilicon gate CMOS at a 1.5 um channel length or below. NMOS processes were shut down one by one. It must have been incredibly hard for the likes of Atari and others to still find a silicon foundry to make wafers for their long obsolete NMOS custom ICs which were designed in the 1970s. Commodore did not have that problem as they had that old spooky and decrepit Ex - MOS Technology wafer fab in Norristown, PA, with its already leaking toxic waste tanks (it's now a "Superfund" site). Apple just switched to the 65C02. In other words, when the problems with the 6502 bus timing began to pop up, the NMOS 6502 was already on its way out. But we still have to use it . . . for "authenticity".
Wow, what a long post with my mind wandering all over the place. But I hope the information I have given in it will enlighten those sorcerer's apprentice types which did not yet fall into this trap. I did, back in 1988. And it cost me a lot of money and a lot of PCBs had to be thrown away.
So the problem is real. It's lurking for you and it will bite you if you don't know how to dodge it. Ironically, DRAMs with their strictly timed dynamic logic are immune to this specific issue with the crumbling addresses. This is why I chose DRAM for my 56 kByte card for the Apple-1 seen here:
Comments invited !
- Uncle Bernie
I made one of these today for my R1+ with P-LAB SD card. It sure makes the thing look nice, and less like a big capital letter 'L' when it's on my desk. No passives/optional components installed.