How bad are MK4096 chips... well let me tell you

I had good luck with a ND Nuclear Data RAM Board (board # ND-ORM 50-1089-00) with three banks of 16 Mostek MK4096N-11 with 7650 date code. All 48 tested ok.

Uh oh, is Unicorn sold out? I've been procrastinating…

Interesting. I hope not. I just ordered some and they were listed explicitly as "MK4096". At $5.99 apiece, they're certainly priced like they're the real thing.

Same for me, Unicorn sent me MK4096N-16 with date code 7726.

My experience is that you have to take some care of the cycle time. The original board uses MK4096N-11, which has a cycle time of 500 nsec, whereas the MK4096N-16 supports a slightly shorter cycle time of 450 nsec. I needed to adjust the 27K resistor at B2 down to 22K to get the MK4096N-16 reliably working. Of course also the real value of the 47pF capacitor goes into the calculation of the Apple-1 memory cycle.

Hi, for my MIMEO project i sourced (new old stock?) Mostek MK4096N-6 chips locally. Reading through this post i am now unsure whether i can really use them. Can you please let me know your thoughts?

They are saying they still have >300 pieces on stock. If somebody else is looking for them just send me a PN...

thank you 

Denis

Ansgar wrote in post #6:

" My experience is that you have to take some care of the cycle time. The original board uses MK4096N-11, which has a cycle time of 500 nsec, whereas the MK4096N-16 supports a slightly shorter cycle time of 450 nsec. I needed to adjust the 27K resistor at B2 down to 22K to get the MK4096N-16 reliably working. Of course also the real value of the 47pF capacitor goes into the calculation of the Apple-1 memory cycle. "

According to my experience, the 480ns timing spec for the 74123 /CAS timing oneshot as seen in the Apple-1 manual is correct, but for faster DRAMs and slower 6502 it may be a bit early, so the 6502 may not have the write data ready yet when /CAS comes. I also found out that the main culprit for the /CAS timing deviating from the 480ns is neither the R nor the Mica C, its the 74123 itself. Mica caps typically have very tight tolerances around 2%. The carbon composition resistors always have been junk, and this is exacerbated by age. I found several with a resistance way too high for the 10% tolerance spec, and these were Allen Bradley ones made in the 1960s, still sealed in the original factory bag. I suspect they deteriorate over time, possibly developing internal cracks or grain boundary rot within the carbon composition mass. The only safe way to use them I have found is to measure them, reject the out-of-tolerance ones, then heat the survivors on one leg with the soldering iron for a few seconds (as in soldering) and let them cool down again to RT. Then measure them again and if the resistance has changed too much from what it was before the thermal torture, they also are suspect and need be discarded.  For builds where I don't need authentic looks I use modern metal film resistors for the timing, and of a value that has been determined with a 50K trim pot in the same build using the same 74123 (actually I use 5K fixed + 50K trimpot in series to avoid any possibility of damaging the 74123). I adjust the trim pot to get 480ns and then power down, pull the 74123, and measure the resistance between pins 16 and 15. The nearest higher value goes then replaces the trimpot, and all is fine. If I have to use the dreaded carbon composite resistors for authentic looks, I select the best fitting one (they have  tolerances wide enough to always find one that fits) but check it again after soldering it in and after its has cooled down.

The interesting find with this procedure was that the 74123 cause most of the deviations. In the past I ended up with R's between 22K and 25K to yield 480ns (the C being selected to be spot on), but the last tube of 74123 I bought, which were newer, needed R's of 20K, and very consistently so.

If you have a PROM based RAM test program, you can also determine the go/nogo limits for the resistor and then chose one that is centered in the middle. This does not work too well with a RAM based RAM test program, for obvious reasons.

Hi,

Did you try -6 Mostek? Speed is 250ns, much too fast. I have some -6 here, but didn't try it so far.

Cheers,

Achim

In post #11, achimhb wrote:

"Did you try -6 Mostek? Speed is 250ns, much too fast. "

Uncle Bernie's comment:

As far as these DRAMs go, there is no such thing as "much too fast". There is only one (rare) situation when you have a very slow 6502 (i.e. 1975/76 date codes, I never found out when the mask shrink at  MOS Technology was done) and if this 6502 presents the write data too late to the DRAM, and the /CAS falling edge comes too early for that data, the write may fail because the wrong (not yet ready) data will start to flip the selected bit line in the wrong direction. If this happens you would need to increase the 480ns oneshot pulse width to place the /CAS later in the CPU cycle. Alas, this bites into the DRAM read access time / 6502 data setup time during CPU read cycles. So ideally, a proper DRAM controller would do early read /CAS pulses and late write /CAS pulses to both get the read and write timing right. The Apple-1 circuit design tries to find the same "sweet spot" for both, using the same timing, which according to my analysis works OK for faster 6502 which present the write data earlier.  Ironically, a slower DRAM may mitigate the write timing problem by being too slow to screw up the internal bit line in the memory matrix. The wrong data may start to move charge away (or add charge) but the right data would come along and stop / reverse that before it's too late. All this depends on fine details of the inner working of particular DRAMs. They are not alike. Every manufacturer has their own circuit level solutions and some may be more robust for one timing violation but less robust for another timing violation.

Over the past year I got a lot of feedback from builders of my kits and also from a few people who tried out my "reliability" mods and if you look at this as an experiment, it succeeded, the builds work, but one interesting fact that emerges from the mist is that for some DRAMs the added bypass capacitors do the trick, and other others, these are not needed (at least when using the higher performing little blue boxy bypass capacitors in lieu of the brown disc bypass capacitors, the ceramic materials and the inner construction is different), but the six damping resistors on the multiplexed address lines are needed to get a robustly running build.

I can't say anything about MK4096 as I never had specimen of them, but for the 2nd generation 4k x 1 DRAMs of the generic  "4027" type I have empirical evidence that Motorola tend to need the added bypass capacitors alone (no damping resistors needed), Intersil tend to need the damping resistors but no added bypass capacitors (even when using electrically inferior brown disc bypass capacitors) while Mostek are generally more robust and in many cases need no reliability mods at all for a decent MTBF ... this means they still may throw a DRAM error after a few days running diagnostics all the time. Good enough to demonstrate this Apple-1 to friends or at VCFs. And a great improvement over Lisa Loop's story that her original Apple-1 rarely ran for 45 minutes without crashing, before Woz "fixed" it, but even the wizard himself could not drive out all its demons: according to the Lisa Loop story it just crashed less often. Would be interesting to have quantitative data on that: was the improvement 2x, 3x or whatever for MTBF ? Woz later gave her one of the first Apple II which remedied the problem once and for all. If you study how the Apple II generates the DRAM timing pulses you will understand why.

With my reliability mods in place, all "4027" type DRAMs from all manufacturers and all speed grades work perfectly robust, these can run diagnostics 24/7 for weeks and months without a single failure. All this, of course, when the 480ns timing is right, and you also need to consider that I furnish my kits with 6502B CPUs that are fit to run at 3 MHz and this relaxes the DRAM timing greatly: the write data from the 6502B comes much sooner and the read data from the DRAM can come much later and the 6502B still can understand it properly.

So this is the path how to get 100% rock solid Apple-1 clones that work reliably. For Apple-1 originals with the slower 1st generation 6502 before the mask shrink I have no experimental data because I have no such machine. But from theoretical analysis based on the original datasheets of these parts it must have been a bitch. And I'm quite sure the same principles apply as for the 4027: there is a narrow timing window in which it may work, and all the ICs in the various signal paths may conspire together to miss that window. For some lucky combinations there is no problem, but for other combinations, it gets wonky. The ringing supply lines and the ringing multiplexed address lines may exacerbate the problem. I think that the Apple-1 in its original form was barely manufacturable. This foiled my plan to produce 100 of them by industrial wave soldering (there were some other obstacles, too, hard to find ICs and PCB being too expensive). But in the past 2 years a lot of progress was made with understanding the nature of this beast and how to tame it and feed it, and keep it performing happily.

Comments invited !

Thank you Corey and Bernie. 

I would never mix different RAM chips. 

The 4027 are very populare as a substitute. I saw it even in original Apple-1.