RAM2E - 2MB RAMWorks-compatible expansion for Apple IIe

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RAM2E - 2MB RAMWorks-compatible expansion for Apple IIe

As mentioned in my "five new open-source Apple II cards" thread, my friend and I have developed some new Apple II card hardware, so the first one I figured I'd try to finish is the RAM2E (GW4203) for Apple IIe. This card goes in the auxillary slot and adds 2 megabytes of bank-switched RAM, switchable by writing the RAM bank address into the softswitch at C073.


Here's the board picture, same as I showed in the other thread:


Here's a timing diagram and the logic equations I've written to implement the timing and to replace the 74LS245 and 74LS373 required to make an extended 80-column card and other RAMWorks-compatibles. I used a bit of an idiosyncratic pseudo-verilog-type way of expressing the equations. Hope that's understandable enough. Soon I will write some real verilog and compile it for the CPLD.


The timing diagram merits a little explanation. The five signals on the top, below the C14M clock signal (PHI0, C7M, nPRAS, nPCAS, and Q3) are sent from the Apple II as inputs to the card. These signals in combination allow the particular state of the CPU/video cycle to be identified uniquely. There is no state counter. Instead there are some signals dictating what to do which are registered at the rising and falling edges of the 14 MHz clock: GateCRAS, nRefRAS, nRefCAS, GateWE, and HoldRow. Together these combinationally form the outputs to the DRAM: nRAS, nCAS, and nWE. This arrangement allows a CAS-before-RAS refresh cycle to occur prior to the video access portion of every 1 MHz cycle. The row address is latched on the falling edge of nPRAS as input from the IIe. Latching of the RAM bank address is accomplished at the rising edge of C14M in state 10100 (see the state bitvector definition in the timing diagram image) when the C07X signal is active and the latched row address (low-order address byte) is 0x73. The rest of the logic equations just implement the 74LS245 and 74LS373 on a typical extended 80-column card.


Of course, the schematic is attached. Since this card does not have software, we may refrain from releasing the board layout, at least not under the GPL... my feeling is that people should do their own board if they wanna sell it, but I would like to make the board layout available to people who want to acquire the parts and assemble their own. Or I could sell bare boards at cost. We will see what people want and probably just do that.


I have not yet compiled these logic equations in Altera Quartus II for the EPM7128 CPLD used on the board. Actually, I don't have a IIe, but I figured I could make a little contribution with this RAM board. So I will have to pick up a IIe soon to test the card with.

PDF icon RAM2E.pdf210.09 KB