How slow is too slow?

In my debug of the Verilog 6502, I noticed that the code was not cycle accurate with the NMOS 6502. A lot of common instructions take an extra cycle. The means that most of the time it will be running 25% - 33% slower. For me, that is unacceptable. I have been playing with writing a cycle accurate version. It is doable, but it will take a lot longer. So I am going to put that on the back burner in favor of getting the APPLE to boot. I will have to make sure I use just the 6502 ROMs. I am in progress of writing a bootloader that will read the ROMs from the LPC Flash device and put it into RAM. I really need to write the keyboard section. The PS2 interface is already finished, but the conversion from scan codes to ASCII needs to be completed. I also need to check the default keyboard key rate. The PS2 keyboard puts out multiple key pushed messages which might affect the way the APPLE reads them. I believe this is a minor issue. The serial port and IDE/ATA interface can just wait until later. I also need to program the Flash device with the ROM.


mmphosis's picture

Greetings, I have been following your progress. On your site you mentioned "The original plan was to buy a 6502 compatable processor from Western Design Center. But I found a VHDL 6502 core on the internet and now have it working." Would it be prudent to go back to this original plan? It might free up some coding space for the Apple II hardware simulation. Rather than using the Verilog 6502 code instead let a 6502 do the processing. If I am not mistaken, the cost of a 6502 is under $5. Just a thought.