I'm studying the Apple 1 schematic, Terminal Section, just to see if I can describe in detail to myself exactly how it creates the composite video signal for a TV. (I'm a retired EE and haven't been able to find a circuit description)
I'm stuck at D11, the 74161 binary counter which (from the context of the drawing) creates a character rate signal from a dot rate signal.
Since the Q3 output is feeding the enable inputs CET and CEP, as well as the "load" input PE (active low), it appears that, regardless of the state of Q3 when the chip powers up, it won't count, or it won't count very long.
If Q3 is initially low, enable inputs CET and CEP are also low, and at the next clock pulse, counting is disabled, and because PE is also low, Q0 and Q2 are set to low (P0 and P2 being permanently grounded), setting the counter to either 0 or 2, but since there's no change in Q3, nothing further happens on succeeding clock pulses, because the counter is disabled (enable inputs CET and CEP still low).
If Q3 is initally high, counting is enabled (enable inputs CET and CEP high), and it will count anywhere from 1 to 8 clock pulses (input CP), depending on the initial state of Q0, Q1, and Q2, and then, when Q3 goes from 1 back to 0, CET and CEP go low, disabling counting, PE goes low, presetting Q0 and Q2 back to zero, and nothing further happens on succeeding clock pulses. What am I missing?
Inputs P1 and P3 to the 161 float to 1's so the counter presets to 1010 (A). The count sequence then goes A, B, C, D, E, F, 0 then starts over at A giving a repeat count of 7 so the Q2 clock output is 1/7 the dot clock.
You're a genius, thanks! So there's 2 dot positions between successive characters. Have you studied this circuit? I'll probably have more questions before I'm through. Thanks again!