Major Issue

I was hoping to be able to run the system at 16.67 MHz just like the OSI system. But just like the original Apple ][, the video has to read the memory interleaved with the processor. The 16.67 MHz, is 50 MHz / 3, with two 50 MHz cycles for the processor and one cycle for the memory. Preliminary testing of the APPLE ][ text video is not stable at 16.67 MHz. Even at 12.5 MHz (50 /4), the pixel clock and the CPU clock have to be syncronized.

The OSI was able to run correctly because of the Xilinx dual ported RAM. But since main memory is not dual ported and the Xilinx built in memory is not big enough for all video modes, the video must interleave with the CPU.

By forcing the CPU clock to allow a two cycle memory read for each of the 40 characters, the video is able to read the memory correctly. The video is now stable. This of course, slows the effecitve clock speed down. The delay is one extra 50 MHz clock every nine CPU cycles. So for every 9 CPU cycles, the 50 MHZ runs 28 sysles instead of 27. The effective clock is 50/(28/9)= 16.07 MHz. This is still 16X the original APPLE ][ Speed.

The Video reads the memory 16 bits at a time. In 40 column mode, the extra buye is not used. But in 80 column mode, the extra byte will be the other character. Since both bytes are read at the same time, the extra delay is the same. The clock speed will not be effected by the video mode. This is true for text modes and graphics modes.


The text video is now working correctly at all CPU speeds. The memory mangling that Woz did for refreshing DRAM has been duplicated.

I am testing the video using the OSI BASIC.

Glenn Jones found schematics for a cache based 6502 accelerator for the Apple II... check out comp.sys.apple2 newsgroup