ram refresh cycle details?

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ram refresh cycle details?

the manual says "Four out 65 cycles is dedicated to memory refresh", does that means that phi2 runs for 61 cycles and then halts for 4 ? Or is it something more granular, like run 15 halt 1 ... ? Which part of the schematic is dedicated to the /RF signal ? I wasn't able to locate it.

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About the Apple-1 DRAM refresh:

Refresh in the Apple-1 is non-transparent which is a big problem if you do tightly timed code (such as in a Woz Machine based floppy disk controller). To be able to pull that off, I had to study the Apple-1 refresh system throughly.

 

Refresh cycles happen during the same time slots on the TV scan line where each 10th character is displayed  (horizontal counter state $C9, $D9, $E9, $F9 (the $ meaning "hex"). This is the "10H" (aka "H10") signal combined with the H6 signal. Remember, the lower 4 bits of the horizontal counter are a 74160 decimal counter while the upper 4 bits are a 74161 hexadecimal counter.

 

If both "10H" (aka "H10")  and H6 are "1", the NAND gate in processor section schematic area D-7 asserts the /RF signal (active "0") and this suppresses the PHI2 phase of the 6502 clock. The 6502 then thinks this is a long PHI1 cycle. And on the next CL clock cycle, the /RF is "1" again, and the normal PHI1 and PHI2 cycles are there.

 

During the refresh cycle, the refresh address coming out of the horizontal and vertical counters is put on the lower 6 address lines of the system address bus  (by multiplexers B7 and B8). And the R/Wbar signal is manipulated to be "0", so any refresh cycle looks like a write cycle. This may appear to be dangerous but it isn't as the /RF also blocks the 74154 master address decoder, so nothing gets activated. As ugly as this trick is, the R/Wbar = "0" also blocks the 7410 NAND gate in schematic area B-4 so the 8T97 tristate data bus drivers stay turned off. The 6502 may activate its own data bus drivers already during PHI1 of a write cycle, so this trick prevents a clash on the data bus of the motherboard.

 

The really nasty thing with this nontransparent refresh is that it "slides" all over the place (referring to a 32 cycle or 40 cycle timed loop as used in the Woz Machine to write normal disk nibbles and sync disk nibbles), so any easy remedy is not possible. Otherwise you could make a simple stop/go circuit for the 6502 which synchronizes the timed loops to the refresh. But 4 refresh cycles per 65 clock cycles don't have a common divisor with 32 or 40 CPU cycles so this simple remedy would not work. I had to invent a PLD called the "TFC", or "Time Flux Compensator", to fix this issue. Not to be confused with the "Time Flux Capacitor" in the DeLorean based time machine of the movie ;-)

 

 

 

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thank you

thank you very much, now I get where the "65" number comes from, it's a scanline time (455/7).

I've implemented that in my FPGA which has now a very accurate emulation. And by the way, I've also implemented the "crosstalk faint dots" you described in another post, for a realistic look and feel! I love them!

 

 

 

 

 

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About the faint crosstalk dots:

In post #3, nippur72 wrote:

 

"I've also implemented the "crosstalk faint dots" you described in another post, for a realistic look and feel!"

 

Uncle Bernie cheers:

 

This is great news, nippur72. This level of accuracy of emulation is much desired. I love these dots, too, not only because they are a truly lovely (harmless) quirk of the Apple-1, part of its unique "personality", but because they help me a lot to diagnose certain issues with bad ICs, in cases where the Apple-1 is so "broken" that the screen output upon start of the diagnostics PROM is just a mess (or does not appear). The integrity of the faint dot pattern allows me to tell that the whole timing chain of that crippled machine is OK and so I can focus on other sections of the circuit. If there are certain irregularities in that dot pattern I can immediately tell which IC is the culprit. 

 

So this lovely quirk is a true advantage !

 

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