Does anyone have Apple 1 oscilloscope pictures (timing) ?

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Does anyone have Apple 1 oscilloscope pictures (timing) ?

Hi there, I am a newbie to this site and I'm trying to get my Apple 1 replica (NTI based) to work.

Video section did work immediately, except the character field seems to be a bit too much to the right, could be the monitor though.

DRAM does not work yet. The lower bank passes Mike Willegal's RAM test as long as the $EXXX bank has empty sockets.

It does not seem to be a problem with the !CS signals, and all the other signals on the DRAM are the same for both banks.

Board has been checked, no shorts or hair cracks, perfect soldering, bypass caps in every DRAM socket.

The 74123 one shot set to 480 ns.

I tried to get some more insight by searching this site with "Apple 1 DRAM", but found nothing that would help.

Maybe the timing of the whole machine is off due to some unknown issue with the 40+ years old chips.

Does anyone happen to have oscilloscope pictures how the timing of the Apple 1 should look ?

For the video issue, a snapshot of a horizontal line including the sync and some characters on the left hand side would help.

For the DRAM issue, CPU PHI2 vs. RAS, CAS would help. The row/column strobe to the 74S257 perhaps, too.

I think such scope traces taken from a known good Apple 1 replica could help me and other builders.

Any timing violations due to faulty TTLs must be ruled out before digging into the more elusive topics like reflections etc.

Anyone here knowing where to find such pictures with the correct timing or able to post them here ?

Maybe I'm asking too much, but I am no beginner with vintage computers and never saw such weird behavior of the RAMs in any other machine. The very same DRAM chips that work in the lower bank fail in the upper bank.  Despite the !CS signals look OK (no clash). All signals of course look terrible as would be expected from this layout driven by 74S logic, lots of reflections seen, but none looks bad enough to cause the DRAMs to fail. I would hate to spoil the authenticity of the build by putting termination resistors in.

Lots of questions, I know, but any hint is much appreciated.







Last seen: 4 hours 30 min ago
Joined: Jun 5 2008 - 07:26
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If you can run it, what are

If you can run it, what are the error codes that the ram test shows when you have both banks populated?






Last seen: 2 days 12 min ago
Joined: Apr 1 2020 - 16:46
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DRAM works now !

Mike - thanks for offering your help, but in the meanwhile, I could get both DRAM banks to a state where they seem to work well enough to pass your RAM test and to run BASIC. Thanks again for your fine RAM test program, which helped a lot. I would have some suggestions for improvement, though, if you are interested, please contact me via my account.


Last seen: 2 days 12 min ago
Joined: Apr 1 2020 - 16:46
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Apple I replica DRAM works now, still would need timing info

My solution was to solder six 390 Ohm pulldown resistors from the A0...A5 address lines at DRAM W7 to GND.On the PCB backside, to hide them. Bingo, all DRAM tests did pass !

Conclusions / hints for other builders:

Looks as if it's a bad idea to drive that ratsnest of a PCB layout with Schottky TTL. Lots of reflections and poor signal integrity. But initially it seemed as if the signals, despite looking ugly, were not too terrible to cause the DRAM failures. A fallacy. See my first post.

I used 41 years old MCM4027AC3 DRAM chips in Cerdip packages which according to the datasheet(s) should work fine in the Apple 1. It could be that those Motorola parts happen to be just a little bit more sensitive towards poor signal integrity than other types of DRAMs, which may explain why other Apple 1's (the originals and the replicas) did work better (?). If they ever were reliable. Take the Lisa Loop story from Tom Owad's book "Apple I replica creation". It tells the tale that even the Woz himself could not get Lisa's Apple 1 to work well enough for her kid's BASIC class, although he was able to improve it such that the crashes happened less frequently and he later generously gave her one of the first Apple II for free.

Other than the poor signal integrity on the DRAMs I found another weakness related to Apple 1 DRAM timing: the 27K resistor R28 at the 74123 oneshot at PCB location B3 should better NOT be one of those vintage carbon composite resistors. These were terribly unstable even when new. If you solder them they change their value much, sometimes dramatically so. They are junk. Use a metal film resistor instead, after determining the right value with a trimpot. The 47pF mica cap on the same oneshot is a good choice, very stable, very low tolerance, do not substitute it.

I'm still wondering how robust / reliable a typical Apple 1 may be, original or replica. It seems to be quirky. Whenever I switch my nearby Weller WTCP-S soldering station on or off, the machine crashes. Verified not related to any DRAM issue, as it happens even with PROM only test programs that use no RAM at all. Still have to figure out how that pulse gets into the machine. Definitely not a military grade design able to work in any ECM environment ;-)

These were the glorious days of the mid 1970s where microcomputers weren't under the thumb of the FCC and could transmit and receive wireless signals on all frequency bands ... no wifi TX/RX subsystem needed, it's all there already, built right into the PCB traces ... /sarc off

Still I would be grateful if anyone on this list could snap and post the previously mentioned oscilloscope photos taken from a known good Apple 1, original or replica. Would stop a lot of builders (not only me) from worrying about possible hidden 'features' that may be caused by those ratty 40+ year old ICs. Many hobbyists think ICs stay fresh forever if not being used. Any semiconductor industry insider knows this is not the case. Lots of failure mechanisms even during storage.

Last seen: 4 hours 30 min ago
Joined: Jun 5 2008 - 07:26
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You may be experiencing known

You may be experiencing known issues with the -5 volt supply.  Check out these two blog posts which include some scope images.


I have found the reliability of the Appe 1 can be very dependant on the type of .1 uF decoupling caps that are used.


Think you are encountering issues now, the cassette interface might (or might not) open a whole new can of worms for you.



Mike W.



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Joined: Oct 9 2011 - 12:54
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The original Byte Shop Apple

The original Byte Shop Apple-1 used Bel .1 caps.  These were very high end caps used in HiFi stereo systems (don't confuse this with the fact that MITs used low end radio caps and parts in their stuff).  The Bel caps are highly stable and do not introduce a lot of noise.  The NTI boards used cheaper caps but ones that were a different technology and thus more stable than typical single layer ceramic caps.


One thing to note,  yes the Apple-1 is very particular to which brand or type of ram chips you use because the timing spec is wrong for refresh and depending on how tollersn5 the ram chip is, you may have a problem.  There was actually a misprint in a data sheet so Woz specified the wrong resistor/cap for the one shot.  Simply changing the resistor or cap can improve reliability and allow the use of less compatible ram chips.



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Joined: Apr 1 2020 - 16:46
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Lionel's mods plus some others improve DRAM even more !

Based on the suggestions and links you provided, further progress was made with my Apple I build, but I am still not at the end of the tunnel (where it works reliably).

In my humble opinion bringing up an Apple I with the hope that it will run reliably and stable in the end feels like being a doctor treating a multimorbid patient. Proper diagnosis in both cases is very difficult as there is no single root cause for all the problems / symptoms seen. In the Apple I, it seems a lot of different little quirks conspire to make it somewhat unreliable, a common ailment of many hobbyist computers of that era. Fix one of the quirks, such as adding another bypass capacitor here or there, and the memory test failures or crashes happen less frequently. Mine had the problem of grossly unreliable DRAM, as decribed earlier in this thread.

After adding the termination resistors on the DRAM's multiplexed address lines, I could get both banks to pass Mike Willegal's RAM test ... for a while. Victory declared too soon. One by one I eliminated "bad" DRAM chips until I was down to 15. From my tube of twenty, five occasionally did fail in any position, after some 5 to 30 minutes of testing.

Then I implemented Lionel's mods as per :

and added a few -5V(VBB)  to GND bypass caps (100nF radials, SMD in glass tube type) at some DRAM sockets and then even those "bad" DRAM chips would work fine for many, many hours ... until they fail again. Aaaarg ! Still, a significant progress in terms of  DRAM MTBF was made.

This despite all of the medicine and witch doctor tricks were applied. So I only have 15 working DRAM chips at the moment and can't even run a complete memory test anymore. I have ordered more DRAMs of the same type (which may turn out to be a mistake) to find out whether it's really those five "bad" chips or if it's still residue of the original lack of bypassing issue, or just the wrong DRAM substitution (although Motorola claims in the datasheet their MCM4027A is "compatible with the Popular 2104/MK4096/MCM6604", the MK4096 being the one in the Apple I schematic).


I will keep you all posted about my progress, if any.


Conclusion (for now):

What a can of worms ! Still, it is possibly one of the most fun projects to kill all the spare time available thanks to COVID-19. Lots of fond and sweet memories of the 1970s coming back ! This is an experience you won't get with any of the Apple I substitutes based on modern chips. Those lack the look & feel. But if they are destined to be hidden from sight in some cabinet, preferably handmade from wood, they may be the easier route without the grievances. Or buy yourself an Apple I replica that was built by somebody who knows how to make them work. At the moment there is one for sale on Ebay (no, not me . . . I'm not yet in that elite club who can build actually working Apple I replicas. Mine almost works.).

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Some more results from DRAM tests - systematic bad address !

Received the new bunch of fifty more DRAM chips I had ordered, took one, plugged it into the empty socket to get back to 16 chips / two complete banks, and ran Mike Willegal's RAM test program for days and nights. No futher DRAM failures, all pass.

Then I ran a DRAM test program that resides in the upper bank and tests the whole lower bank. It can so that because it does not use any zeropage and stack operations, only the CPU registers (tricky programming). This test found another bad DRAM chip failing at location 0x0237 which Mike's RAM test did not test. After replacing that chip and running various RAM tests again, I found no further bad DRAM chip even when running DRAM tests for hours.

Still, the whole DRAM issue needs further investigation. All the "bad" DRAM chips fail at that address, or the equivalent address 0xE237 of the upper bank. Now I have eight of those "bad" chips. Highly unlikely that each and every allegedly "bad" DRAM chip has a bad bit cell at the same address, so it may not be the DRAM chips who are the root cause. They just may be willing conspirators, some of them being more sensitive to the root cause than others.

If we convert 0x237 to 12 bit binary:0010 0011 0111and then split it into groups of six bits:001000 | 110111and then write that in two lines:001000110111we can see that all the DRAM address lines do toggle.

Which may be the reason why this address is more likely to produce errors than others, and although there are more addresses where many (or all) bits toggle, this address comes earlier and thus preempts the possible errors onthe following addresses. I'm now looking into writing a DRAM test program that emphasizes these "maximum toggle"addresses.

Here is another cute program that can be used once the Apple I build runs well enough to load and run BASIC:

10 S = 020 FOR A = 4097 TO 819230 S = S + PEEK(-A)40 IF S < 30000 THEN 6050 S = S - 3000060 NEXT A70 PRINT S80 IF S = 19774 THEN 1090 PRINT "FAIL"

It creates a checksum over the upper bank where the BASIC interpreter resides. I assume (without further proof) that BASIC runs so slow that the loop reading the RAM won't substitute the hardware refresh. So if there is an issue with refresh that affects DRAM reliability, the BASIC program should complain or crash (the latter possible if DRAM failure corrupts the interpreter). If the DRAM works OK, it should be able to run for days without interruption.

On my machine, it ran fine the whole day but crashed somewhere in the night. It still had the courtesy to spit out a "STOPPED AT 40" message before the BASIC interpreter died completely, taking no further commands. Quick examination with the WOZmon showed that many bits of DRAM chip W7 had been set. Funny. I have no explanation for that yet. The chip at W7 was replaced by a fresh one. Now the whole DRAM test procedures have to be done again.

Maybe I shouldn't have been so thrifty to buy cheap "pulls" for my DRAMs. But other than being cheap, they have Cerdip packages, which is the best package there is other than MILSPEC inert gas filled sidebrazed ceramic.Cerdip packaged chips, if proper procedures were used in the packaging process, and properly stored, should last for centuries if not millennia. Those in plastic packages, not so much.

I will keep you posted about any further findings !

P.S.: There are still a lot of things to investigate and fix - seems building and bringing up an Apple 1 is a real endavor that is not for the impatient or faint hearted. I wonder how many builds had less teething troubles than the mine. I will open another thread soon to find that out.


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Hi Uncle Bernie!

Today is Forgiveness Sunday - in Russia everyone asks everyone for forgiveness, both for past grievances and for future ones. Very comfortably! Forgive me - you have to say God will forgive.


I began to slowly reread all your posts from the very beginning. Now you are already far ahead, but suddenly it will be useful to someone else in the future. Unfortunately, I can’t comment on these screenshots from the oscilloscope, I haven’t seen it in my eyes and have never held it in my hands, they were provided to me by a friend from Italy. Please note the DATA/ ADDRESS BUS is just an example of some kind of activity and should not be taken as a reference. On the other side, all the other signals are quite cyclic and your signals should not be too different.



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