How important are the IWM features for the Apple IIc ?

In post #9, rjustice wrote:

" This simplifies the code as its not needed to be cycle accurate to keep feeding the IWM data every 32us ".

Uncle Bernie comments:

True that. Getting the write timing right in synchronous mode is tricky, especially if you use 6502 vs. 65C02 and want RWTS code which works on both. Some instructions have different cycle counts on the 65C02 vs. NMOS 6502, and the 65C02 also does no "phantom read" on the STA abs,x instruction which is essential for the original DISK II controller to work properly. Using the asynchronous mode (what a nasty misnomer, they should have called it registred mode, latched mode, or something else) will do the right thing for any version of the 6502, if the code is written properly. But I still wonder how they do the 40 us long "SYNC" bytes in the asynchronous mode. I'm still scratching on the surface of the IWM but I think it's possible to do a PLD based substitute without excessive IC expenditure. Not sure if a 32 MC PLD could do it. A 64 MC PLD is enough, unless the turn off delay timer is done with a counter. IMHO it's stupid to waste so many macrocells just to make a 1 second delay. I will do that with one external capacitor / resistor instead.

Mission objective of my "Replica IIe" project has suffered from mission creep and now also includes the Apple IIc. So there will be extra time and effort required. But I still hope I can do this in a useful amount of time. I don't have four years to waste like the guy who designed the Yellowstone floppy disk card. My scope must be more humble. I have allocated two weeks for a complete reverse engineering and substitute design for the IWM. And I'm not willing to spend more time on that. In two weeks my test run of "Wings of Fury" which runs 24/7 is complete and then I need my spare time to advance the Replica IIe motherboard design, and the IWM substitute must be put on a back burner, if not yet completed at that time. But I do understand that for a complete Apple IIc mode, a complete IWM is needed. Not sure yet if I could take out the 8 MHz mode, which I think was only used in the Mac. The Apple IIc has no 8 Mhz clock on the motherboard.

- Uncle Bernie

I saw the work of "PlamenVaysilov" of post #13, and I'm impressed - very nice solution of the interposer PCB. I will "steal" the idea from you if you show us the backside of the PCB. It seems you only do very small vias down and solder the pin header such that no pin actually comes up to the top side. This seems to be an elegant solution to the problem being that most TQFP packages for CPLDs/FPGAs will not fit between the pin rows of a typical DIL, so making these adapters is difficult ... and Plamen's solution could be the missing piece.

As for the IWM itself, simply I must do my own design, cannot avoid it, because I target much older PLDs, and can't use MachXO parts.   Because there ain't no MachXO parts in my basement, and only thousands upon thousands of smaller, older, PLDs and CPLDs from the 1980s and 1990s. I think that my IWM substitute will be a mix of 74xxx parts and some GALs. Maybe a 7C330. Don't know. I thought I had several 100's of the 7C330 but only found one tube. My mission is partly driven by finding a use for these PLDs I've collected over the part 40 years before I die. Because my worthless heirs will throw them into the trash, along with my lab instruments, my library, and everything else. So I better find a good use for these parts soon ! I'm not the youngest anymore ! (but still healthy enough for a Class 2 pilot medical).

Plamen's mission is different, he obviously sought something which would drop into a real IWM socket. I don't need that. So I can use more ICs.

I did  not build my IWM test adapter yet. But some progress has been made with the design. I found that if using the exact data separator method outlined in the IWM spec, and the IWM patent, it is impossible to accurately reproduce the exact timing (Q3 clock cycle wise) as the original DISK II controller.  This has been proven by simulation and compare of my own DISK II substitutes and the "new" design. The final contents of the read register however is the same, as long as the disk bit stream is not pathological and conforms to Apple's GCR rules. But the read byte may appear a few Q3 cycles later than in the DISK II. I do not know yet whether this difference matters. For normal floppy disks, it won't. But for copyprotected floppy disks using weird copyprotection methods it may make a difference. This must be investigated. I could put both state machines into my substitute, and use the original one for 7 MHz SLOW SYNCHRONOUS mode exclusively, and the data separator and shifter method of the real IWM for all other modes. This would guarantee 100% compatibility with any copyprotection that works on the original DISK II controller. For me, DISK II compatibility is of the utmost importance. It takes priority over a faithful 1:1 reproduction of the original IWM. But it is understood that the "added modes" of the original IWM also must work. Such that the result could be used in a Mac, too. Just in case.

Here is a riddle:

As said, the test rig is under construction, so I can't do hardware investigations yet.  I'm still trying to understand Apple's documentation. It is quite complete (U.S.-Pat. 4,742,448 naming Wendell Sander and Robert Bailey as inventors supplies fine points which the IWM docs found on the web don't tell).

But what I did not understand so far is how the IWM produces the SYNC bytes (bit cell sequence 0011111111) in its asynchronous mode (the "Mac" mode). In the synchronous (legacy) mode, it works like the original WOZ state machine of the Disk II controller, it just shifts "0"'s into the shift register during all writes, so if the software timed shift register reload which should happen all 32 CPU cycles does not happen, but happens after 40 CPU cycles, with a $FF value, than the SYNC byte bit cell sequence 0011111111 is written out to floppy disk. The two "0" of which a re coming from the empty shift register, and the "1"'s are coming after it has been reloaded with all "1"s.

But in asychronous mode, this programming approach is not possible. Because if the write data latch has not been written in due time (within the 32 6502 CPU cycles from the last write), the write underrun flag is set and the whole write operation is terminated deasserting the write gate signal. Actually, this is smart because a crashed or interrupted write routine will not ruin / overwrite the data of a whole track. But it thwarts the generation of SYNC bytes using timed loops. The only way I can see to still write SYNC bytes in asynchronous mode is to write them as a sequence of byte values like this:

1st byte:  00111111 (violates Apple GCR rules by not having MSB set, but does not harm anything)

2nd byte:  11001111

3nd byte:  11110011

4nd byte:  11111100

5nd byte:  11111111

6th byte:  00111111 (same as 1st byte, five byte sequence repeats from here)

Bytes 1 to 5 above produce the same 0011111111 0011111111 0011111111 0011111111 sequence of SYNC bytes on the floppy disk as the legacy method would do with 4 shift register loads spaced 40 CPU cycles (on the 6502) apart, but as we can see, it's only possible to write groups of four such SYNC bytes and not violating any of Apple's formatting rules, which is a limitation compared to the legacy DISK II controller.

This limitation could be overcome, though, by more elaborate programming effort, setting up the byte stream to the IWM with arbitrary bit boundaries. The 68000 in the Mac sure can do that but to me it looks awkward, inefficient, and would slow down the disk write processes.

So the question asked to the forum members is if anyone has knowledge of the disk write routines or the format specification used in the Mac ? Or can point me to some 68000 assembly code listing of Mac RTWS code to inspect ? (I'm not a Mac guy, buy can read 68000 code).

This is just to verify that there is no "hidden" feature somewhere in the IWM to write SYNC bytes in asynchronous mode of the IWM other than using the above five byte sequence method, which at the moment is the only way I can deduct from the documentation. If there is any other way (other than using synchronous mode) then I need to know it such that I can plan my hardware development platform accordingly.

These are the subtle things you find when reverse engineering based on docs and patents. This means making a plan / crude initial design   before   actually exercising the hardware. By doing so, apparent contradictions or "holes" in the spec / documentation may become more apparent than if using the other approach, just putting the original IC in a test rig and start hacking.

Comments invited !

- Uncle Bernie

In post #21, "CVT" wrote:

" You can just bend the pins of a regular round-contact DIL-28 socket.  "

Uncle Bernie comments:

If you meant a "machined contact" type socket, no, you can't bend those pins, because they will break off.

The same mishap (breaking off pins) would happen with the type of male/male DIL adapter Plamen uses, unless it is done carefully, like he may have done, unless they are off the shelf items already having these bends. It could be done using two pliers, one round nosed one to hold the pin, and another one to bend it. Note that his example bent the small diameter pins which in the unbent exampes of these adapters are supposed to go into the IC socket into which this module is plugged.

I'm very familiar with this type of adapters and they do have issues:

- If you plug the large diameter pins into an regular IC socket, the larger diameter overstresses the contact springs in it and then that socket can never again reliably grip a regular IC afterwards. Regular ICs have smaller diameter pins.

- If you plug the small diameter pins into a regular IC socket, the socket is not damaged, but these pins are so weak that they easily get bent and then break off when you bend them back.

These adapters were used in one of my products in the 1980s which were sold in huge quantitites (10,000's) and consequently we had 100's of returns from customers who broke off a pin. This is why I bought the professional desoldering station I still use today, to be able to repair them. I also had one PCB production run using a new layout where the spacing between the pin rows was wrong and so these "large diameter" pins had to be bent slightly to be able to assemble the product. This did cause some casualties, but still was cheaper than to throw away the whole botched PCB production lot.

Based on my experience with these adapters, I don't think that Plamen's approach is optimal yet. The basic idea is good for a one-off specimen, but improvements are needed until these IWM replacement modules could be produced in larger numbers. This may sound nit-picking to you but if you ever engaged in "mass producing" any ready made plug-in modules for any computer, you know what I mean. Unless your workers are slaves who work for food and shelter (sleep under the work benches) you can't allow any such complications which require manual fumbling / mods of sensitive connectors / etc. and drive up assembly/test/repair costs into the stratosphere.

Professional assembly houses simply will reject such a project.

I think I have some of these adapters around which don't have the large diameter pins but only rows of round, flat surfaces. Maybe these could be reflow soldered flush to the bottom side of a PCB. This would solve the problem with bending the pins. I need to find them in my mess first before I can tell you if these are standard items or were modified by means of a file. Stay tuned !

- Uncle Bernie

P.S.: I just saw Plamen's post #25 stating that he did not bend these pins because these adapters SMD are standard items. It eludes me why they have the larger diameter pins straight so these must go into a DIL socket. It should be the smaller diameter pins which should be straight and go into the socket. I know for certain because I do have lots of various types of adapters around. All have the smaller diameter pins to go into sockets.

In post #31, CVT wrote:

"... off-topic question that has been bothering me for a while now: would it be possible to make populated SMD PCBs small enough to fit inside an empty ceramic DIP package ..."

Uncle Bernie comments:

Not so much off topic when seeking a viable IWM replacement. We have a company in town which makes hybrids in small production runs for the local electronics industry (Agilent, Lockheed Martin ...) and they even can take the die (silicon chips) out of existing packaged ICs. The substrate is ceramic with a custom pattern they design so they can do the die attach and the bonding of the ICs. They use very small SMDs for the passives, like bypass capacitors, resistors ... the resistors look like ground pepper, not like bird feed.

So it can be done. But the costs are prohibitive. One such hybrid can set you back by several 100's of dollars for small production runs, and the engineering costs adds to it. Below US$ 10k, nothing can be done.

For Apple II work this is too expensive. But if Lockheed Martin puts together a rocket to launch satellites and they need some odd IC that was not made anymore since the 1960s then the cost can be justified.

Just another example: suppose you have made a few die for one of the elusive Apple custom ICs. You can get them in waffle packs, so they already are separated. Now mount them into a ceramic package. The service companies who do that for you will typically charge $10 per pin. But this includes the ceramic package itself. So your MMU or IOU will cost you $400 each, and the IWM will cost you $240. This does not include the costs to get the silicon.

It is cheaper to buy an Apple IIe or IIc off Ebay and cannibalize it.

For me, all these little obstacles you encounter in the field of micro electronics if you try to build anything on you own dime was one of the main factors why I decided to work as an employee in the semiconductor industry. With access to the equipment in the company lab you can do a lot of private projects that are financially infeasable if you try to do them on your own dime.  Alone the access to a professional SMD workstation is priceless.  With the micromanipulators and the professional quality stereo microscope you can build really small projects, even with the tiniest components. These workstations are rare and expensive because they are not made in huge numbers. They are only needed for prototype / lab work and are never used for actual production. Much of it is also driven by the desire to keep prototype silicon in house and never send it out to Asian assembly houses. "Ooops - one or two fell to the floor and we could not find them."  --- this is how prototype silicon may end of in the hands of the Communist China industrial spies. It is better to keep all the development work in house until the product is released. Hence, costs for the tools is secondary.

- Uncle Bernie

In post #35, CVT wrote:

" ... but soldered to the empty ceramic package by the hobbyist ... "

Uncle Bernie comments:

If you can find a source for empty ceramic packages. The prototype assembly service providers I mentioned  have them in stock, I know, but they are  not  inclined to sell them to hobbyists because there is  no money to be made  with that. From the manufactureres of these packages you need to order 1000's.

The next obstacle it your proposed soldering process itself. The contact areas on the ceramic package are meant for ultrasonic bonding, not for soldering of any kind. I'm not saying it won't work, because I never tried soldering them, but it will depend on the exact metal layer contruction of these contact areas and on the solder alloy whether it will work or not. The semiconductor industry uses a process similar to soldering in these packages called "Eutectic die attach" (https://mrsisystems.com/eutectic-die-bonding/) and this is not trivial to accomplish in a reliable way.

The last but not least issue is the thermal expansion of your PCB compared to the ceramic package. Unless you use some form of interposer, thermal cycles will build mechanical stresses which sooner or later will crack your solder connections. The same problem exists with BGA packages having no plastic film interposer, like the "CSP" flavor of these packages. IMHO you can't build reliable electronics with CSP which will last for a long time. But probably OK for disposable items you throw into the landfill after 1-2 years of use, when the unreplaceable battery is not holding much charge anymore. Such as "smartphones" which, from the standpoint of unwieldy size, vulnerability to damage, high price, and short lifespan are not "smart" at all, except for the profits of their manufacturers. It's also called "landfill economy".

The general, fatal, problem with microelectronics roots deeper of course. Unlike with ICs of 50 years ago, leading edge ICs of today are so enormously powerful and so terribly expensive to design (1000's of designer man-years going  into each, they are "systems on silicon") and the single digit nm wafer fabs and supporting backend process machinery are so expensive (billions of US$ invested) that these ICs must be produced and sold by the 100's of millions each year to make the whole industry economically viable. There not all too many products which need this kind of processing power and could be sold in these huge numbers. Smartphones and flat panel TVs are prime examples for such a product. So they must be designed and built in a way they don't last. Otherwise the demand for these leading edge ICs withers away and the whole leading edge semiconductor industry goes bust.

There is no way that "hobbyists" can be players anywhere in this league. We will be forever confined to use trailing edge technologies from many decades ago. Until the stocks of these old ICs run out.

I'm not saying that trailing edge ICs are not newly made. They are. Actually, the majority of ICs in manufacturing numbers (but not in numbers of transistors produced) are made in trailing edge process technologies. But unlike the 1980s and 1990s, small startups can't access these processes anymore and it also would be tricky to define a novel product which could be made in these trailing edge processes and still could be sold in large numbers and at a profit to make the whole startup viable. Compare that to the "good old days" of the 1980s and 1990s where small, fabless, outfits could design their own full custom ICs and successfully sell them. Nowadays all you can do is to repurpose some mass produced leading edge IC by putting it on a hobbyist friendly PCB and support it with a development software kit. The "Raspberry Pi" phenomenon explained.

The key words here are "mass produced" and "repurposed". Only then it's viable to get hobbyist (or small outfit) fingers into the deep submicron IC pie. For those not so familiar with the English language, the meaning of this is that the makers of the pie don't want you to stick your fingers in. It is unwanted / discouraged that the unwashed masses have access to high tech other than as a dumb consumer who just pays for it, but does not know anything about how it works. It's a form of enslavement of the masses to their masters / exploiters. Whereas ability to access technology and bend it according to your own ideas and will and purposes (using it for your own ends  not  endorsed by the rulers) is enpowerment of those who have the brains to do it. This threatens the powers of the ruling parasite class. So they decided to make access to technology prohibitively expensive. And here we are.

- Uncle Bernie

Despite we are a bit deviating from the topic of this thread (replacing the IWM) , 'Robespierre' has brought up some interesting topics in his post #37.

As for the "analog IC" topic, I was surprised that nobody can make the  AD590MF  anymore. I think I have a bag full of them in my basement. Will look for them and if I find 100 pcs and can sell them for $300 each, I might have the budget to build an IWM on a real CMOS process ... but this would only yield a few die. Any larger quantity would need much more investment.

There are other super cool analog ICs, too. Like this one:

https://www.eevblog.com/forum/projects/ltz1000-nice-die-pictures/

I can only recommend his website (https://www.richis-lab.de) for everybody  who is interested in the beauty of analog ICs.

The problem with the higher performance speciality analog ICs (like this voltage reference, or the even more elusive LTFLU)  is that they were designed by the true giants in the field who learned their tricks of the trade in the 1960s. These analog IC design pioneers not only knew how to design analog integrated circuits but also how to design (or at least tailor) a process technology in such a way that their designs would reach these out-of-the world performance parameters. There is a lot of "secret sauce" involved in every step towards the final product. The circuit designs may look trivial at rthe first glance (few transistors involved) but may have a lot of tricks in it. The layout has tricks in it. The wafer fab process uses tricks which may be hand dialed in for these lots of special parts. The packaging process uses tricks. Such as little "ball bearings" in the die attach compound, to keep mechanical stresses low. Of course, this needs a package with a hollow die cavity. Special alloys for the package and its pins may be involved, also to keep thermocouple effects low. The trim & test procedures may include pre-ageing / burn-in. And so on and so on.

And only if everything is done right, at every step, the final product will have the stellar specs no competitor can ever reach.

And then the small, boutique IC maker is bought by a larger competitor. The old wafer fabs are closed down and the products are moved to the modern processes of the larger outfit. And then they find out they can't reach the stellar specs anymore. The designers of these rare, super high performance analog ICs have long retired or are long deceased. Nobody knows or understands the tricks which were used. So they can't build these products anymore, even if they wanted. And so these products get discontinued. Pity the customer who needs them and has no replacement in sight.

About the 1980s and 1990s

In the field of microelectronics, these years were unique. Because small businesses (like me, hint, hint) were able to access cutting edge technologies and ICs like the big guys / aka corporations. And so we could run circles around the big guys, being more agile, and able to access markets which the big dinosaurs could not serve. And we made a lot of money from that. It was even possible, back then, to access CMOS processes which were still the workhorses of the semiconductor industry. Ebeam technology did exist --- ES2 (European Silicon Structures) being just one example. No masks needed - you could make full custom CMOS ICs in a 1P2M technology around 1um (IIRC) in small lots, like 5000 pcs, equivalent to 1 wafer or so.

(https://www.linkedin.com/posts/chrisgare_who-remembers-european-silicon-structures-activity-6970428321339744256-CRuW)

Beginning with the mid 1990s all this went away. The 350 nm technology node was too expensive, too  large of a jump, to make for most of the small players. But some services like MOSIS soldiered on and you could get the occasional wafer run on an affordable process. This was great for universities and for prototype runs but as it turned out, all that was viable only for experimental or research work. Once you wanted to make these ICs in useful quantities, it got too expensive too quickly.

If you have $50000-$100000 to spend, you can access modern, cutting edge CMOS technologies even today. But all you will get is a a few specimen of your IC in a waffle pack. Forget the idea to ever get these into mass production (unless you want to spend millions of US$). And yet another obstacle, of course, is that with "free" CAD tools like MAGIC you can't design cutting edge ICs, even if the scope is humble in terms of transistor count (no 100's or 1000's of design man years ;-)

The reason is that the parasitic extraction tools of these 1980s era CAD suites are too weak to deal with the complexities of deep submicron processes. You need extractors based on field solvers to get it done right. I lost track on what a typical Cadence Composer / Virtuoso CAD seat costs per year in terms of license fees, but IIRC it used to be around $100k per year (Universities get the tools cheaper but can't make products with them).

So we are in the inconvenient place we are now (Apple II IC substitution wise). We have to use 30-40 year old PLDs/CPLDs to get anywhere. And we can't make new full custom ICs (although I would be itching to design an Apple IIe on a single IC, low power enough to put it in a wristwatch running on a button cell).

Finally, "robespierre" mentioned what would happen if some cataclysmic event would strike our technological civilization. It does not need to be a big event such as global thermonuclear war. I remember one earthquake in Japan which damaged one chemical plant that produced most of the photoresist used by the worldwide semiconductor industry. We were scrambling to do emergency plans which product lines to shut down to stretch the stock of photoresist we had. It was a huge crisis the worldwide public did not hear a peep of. But the Japanese were able to move the production to another, undamaged plant just in time to prevent the shutdown of the whole worldwide semiconductor industry.

This is how sensitive this whole Jenga tower of "Hich Tech Industry" has become. Oh, and even the Germans can't produce these great mechanical sewing (or knitting) machines anymore. And even the clever Chinese can't reverse-engineer them well enough to get the same performance from their copies. "Secret Sauce lost " strikes again. (in the early 1990s I designed a few custom ICs for a knittting machine maker, so here you have  one of the hurdles for copycats).

- Uncle Bernie