Hey folks, new here. I've been working on an FPGA-based expansion card for the IIe called Byte Hamr. It's built around a Lattice ECP5-85F, and the idea is that different gateware turns it into different peripherals—serial card, RAM expansion, whatever.
I know Carte Blanche exists, but it's a closed ecosystem. I wanted something fully open where anyone can write and share gateware.
I've got PCBs out to fab now. Leaned heavily on the ULX3S open source project for the FPGA power/config side, which gave me enough confidence to pull the trigger. ( Maybe ill-placed confidence )
Honestly, part of why I started this was to learn the bus firsthand rather than just reading about it. So I'm curious—how have people approached testing bus timing and peripheral logic? I'd love to actually probe signals and see how reality matches the theory.
Repo's here if anyone wants to follow along: https://github.com/robertrico/project_byte_hamr
Also working on a companion breakout board (Byte Ravn) that level-shifts the bus to 3.3V for prototyping with Picos and such. Still in design. Open to questions, feedbacks, pushes and especially "have you thought about..." gotchas.
Quick update on Byte Hamr.
Since posting, I've dug into the A2FPGA project and realized there's more overlap than I thought. So worth addressing: why another FPGA card?
A2FPGA is a polished product that does what it does well. Byte Hamr is aimed at a different use case — a prototyping platform for people who want to build their own peripherals from scratch. It has 64MB onboard SDRAM, 12 GPIO pins broken out, and uses 74LVC245s for level shifting instead of a CPLD — less elegant, but still in production.
The tradeoff is that Byte Hamr is very much a "bring your own gateware" situation. Not a turnkey solution.
On the software side, I've been working through 6502 assembly on actual hardware using Merlin, building toward menu systems and configuration interfaces. The A2FPGA repo has been useful for reference HDL, which helps with understanding the gateware.
One thing I'm still trying to nail down: what's the gold standard reference for peripheral timing on the IIe bus? I've got the usual sources (Understanding the Apple II, schematics) but I'm wondering if there's a definitive "this is how compliant cards behave" resource. Planning to verify against real hardware with a logic analyzer once the board arrives.
Is this an Aux slot card?
No, it’s a standard peripheral slot card (slots 1-7).Is it the RAM that prompted the question? The 64MB is onboard for the FPGA to use — my first project uses it as a capture buffer.
Yes, the RAM triggered the thought of a aux memory, video and more. Like BITD but with new HW and more features.
I've moved updates to the VCF Forums - follow there if you're interested. Thanks!
https://forum.vcfed.org/index.php?threads/byte-hamr-fpga-expansion-card-for-apple-iie.1256060/