601, 603, 604: History lesson needed.

These links might help you..

http://arstechnica.com/articles/paedia/cpu/ppc-1.ars/1

http://arstechnica.com/articles/paedia/cpu/ppc-2.ars

While I don't know a lot about the 600 series processors, I do know that the 604e was a killer chip. We still use a 9600/350 at work, and it's one fast machine. In its day people preferred that machine to the G3's that sold alongside it.

In its day people preferred that machine to the G3's that sold alongside it.

That was mainly because it had 6 PCI slots, the G3 only had 3, but it was a very fast chip.

The 601 was a single chip implementation of IBM's POWER1 processor with a Motorola 88000 bus interface. The 601 has 32 KB of cache that is unified between instructions and data. Chips were only made by IBM with clock speeds ranging from 50 Mhz to 120 Mhz. L2 cache was provided by the system's chipset.

The 603 was designed to be light weight, inexpensive cheap from the start. Its floating point unit was not as strong as the 601 but it did integer work better. The 603 had its L1 cache split into instruction and data, each 8 KB in size. The bus design introduced by the 603 is highly related to the bus design used on modern G4 chips. L2 cache was provided by the system chipset like the 601. Clock speeds ranged from 66 Mhz to 100 Mhz but Apple only used the 75 Mhz speed grade in shipping products. The 603 wasn't that great of a performer due to its small L1 cache size. The 603 was made by both IBM and Motorola.

The 603e addresses the plain 603's cache problem by increasing the L1 cache to 32 KB total. It was split into a 16 KB chunk for instructions and 16 KB chunk for data. Outside of the L1 cache, the 603e is basically the same chip as the 603. Some literature refers to a 603ev which is identical to the 603e but manufactured on a more advanced process and higher clock speeds than the 603e. The 603e went from 100 Mhz all the way up to 300 Mh for the 603ev incarnation.

The 604 was IBM and Motorola's prized chip as it offered incredable integer and floating point performance for its time. The chip had 32 KB of L1 cache evenly split for instructions and data. The bus interface of the 604 was identical to the 603 and 603e. Similarly, the L2 cache in a 604 is controlled by the chipset. The 604 went from 100 Mhz in a few IBM workstations to 180 Mhz in a PowerComputing Mac clone.

The 604e is an update to 604 that provides quite a few internal changes. First off, the L1 cache size has been increased from 32 KB total to 64 KB total. That 64 KB divided into dedicated chunks for instructions and data. The 604e adds an additional integer math unit to speed up general calculations further. The 604e was manufactured using more robust tools to increase clocks from 166 Mhz up to 400 Mhz (Apple only used up to 350 Mhz rated chips however). One thing that didn't change was the bus design so 604e upgrades were quick to appear for 604 based systems.

The 750, a.k.a. the G3, arrived to crush the general performance of prior PowerPC chips. It has 64 KB of split L1 cache and a dedicated L2 cache controller. The dedicated L2 cache controller is the main reason for the chip's performance gains but it does have plenty of internal changes from its predecessors for the more technically inclined. The G3 continues to use the same bus design as the 603/603e/604/604e so upgrades are plentiful for older systems. Clock speeds ranged from 200 Mhz 500 Mhz. Motorola and IBM both produced the plain 750's.

IBM has taken the 750 and introduced a few variants (750FX, 750GX ect.) by incorporating the L2 cache entirely. Sizes vary between 256 KB to 1 MB of unified L2 cache. With newer manufacturing technology, IBM has also managed to produce G3 class chips up to 1.2 Ghz.