Hello everyone! My name is Zane, and this is my first post on the AppleFritter forum :). I'm posting to announce the coming availability of my 4 Mbyte Apple IIgs DRAM card, shown below:
Why did I make the card?
Some time ago, I acquired three Apple IIgs systems (along with a bunch of Macintoshes) and have been restoring the machines on-and-off since. When I realized the necessity of RAM expansion for the IIgs (especially the earlier ROM systems), I figured I'd make my own RAM cards, keeping three and selling the rest. If there is continued demand, I can make more. I plan to offer the card for $30-35, fully assembled.
The card provides 4 megabytes of DRAM. The model number is GW4201C... Some other in-progress designs of mine have other numerical designators, and this is the "C" revision of the card. The "A" revision had the logic associated with the RAM implemented in 7400 chips, and "B" lacked the little chin pointing toward the rear ports. Those revisions were abandoned before completion. I never manufactured or tried those ones out.
Two 16Mbit x4 DRAM ICs in (1990's) industry standard SOJ-24/SOIC-24 packaging implement the main DRAM storage. These are shown at the top of the card. I really wanted to use only a single 8-bit DRAM, rather than two 4-bit ones, but 32 Mbit DRAM is basically nonexistent (only even power of two sizes exist), and 64Mbit 5V DRAM is really hard to find. I wanted to avoid putting voltage regulators and level shifters and that kind of stuff on my board, so the largest easily-obtainable 5V DRAM chips were used.
A single GAL16V8-type device implements a bit of special logic required for proper operation of the DRAM ICs. This is the socketed DIP-20.
As has been written about in extent elsewhere, the 1Mbit DRAM spec is slightly less specific than the 4- and 16Mbit spec, and so the write-enable signal coming from the IIgs must be properly inactivated during refresh cycles. My GAL-based implementation of this gating circuit differs from other publicly-available designs in its functionality and implementation. At the beginning of each DRAM access cycle, be it a "normal" RAS-before-CAS cycle, or a CAS-before-RAS refresh cycle, a "write enable enable" (nWEE) signal is latched. Only during regular RAS-before-CAS cycles is the nWEE signal enabled. The GAL device then buffers the nWE signal coming from the IIgs, gating it according to the internally-generated nWEE. For ease of routing, two nWE outputs are produced, with one sent to each DRAM chip.
As well, compatibility with the 16 Mbit DRAM ICs requires multiplexing of the CROW0 and CROW1 signals coming from the IIgs onto a single address line of the IIgs. The GAL does this as well, sending CROW1 when nRAS is inactive, and CROW0 with nRAS active. Hold time of this address bit signal after nRAS becomes active is somewhat adjustable, up to 40 ns or so (the 16Mbit spec requires 10 or 15 ns, as I recall).
Here is a shot of the GAL functionality being simulated in PALASM 4. Shown first is a CAS-before-RAS refresh cycle, and next is a RAS-before-CAS write cycle. The address multiplexing as well as the nWE gating can be seen.
A great deal of attention has been paid to signal integrity. Most of the control lines coming from the Apple IIgs (e.g. RAS, CAS, etc.) are series-terminated, so no termination was necessary for these signals. The address bus, however, is designed to drive some 32 DRAM ICs, and so it is unterminated and has a relatively strong drive strength. Therefore termination is provided for the DRAM address signals coming onto the card. I plan to use at least 33 ohms, but likely more. The aim is to have the lowest drive strength and slew rate but without violating the minimum slew rate spec of the DRAM chips. The single multiplexed address signal coming from the GAL and going to the DRAM is also series-terminated, although the necessity of this is not clear. A ground grid design was used to minimize impedance discontinuities and avoid reference plane crossings. These measures, along with the small size of the card, ensure excellent signal integrity with only a 2-layer PCB.
In a few weeks I will be receiving some prototype units which I will assemble and test. One I'm sure it works, if there is interest in purchasing the card, I will make them available for sale. Also in a week or two I will be announcing another product for Macintosh Plus. Some on the forum may be familiar with my earlier efforts at producing a Macintosh accelerator. Well that work is difficult and still ongoing, but I will be announcing a Macintosh Plus product a bit more novel and interesting than this RAM card.