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Thanks Uncle,
If I understand there are 3 type of emulation:
- DISK II
- DISK3.5
- HD
I am working on the hardrive with the Smartport bus protocol:
When I boot my II GS I receive the following messages
But reading the documentation
with the following adjusted offset
Command 90 means nothing it should not exist !
very very strange
Any clue ?
Using a IIc with a ROM 4X I have the right Message
23:59:59 INFO Core/Src/emul_smartport.c:1246: Dump packet src:81,dst:C3,type:80,aux:80,cmd:85,paramcnt:82
0000: DF 9F E7 F9 FE FF C3 81 80 80 80 81 A0 C0 85 82 - ........808080.....0010: E5 99 E1 80 80 FF 80 FF FF FE C8 C0 - ...8080.80.........
But using the IIGS ROM 1 I does not work by using an init ?
Do I have to do something in the configuration ?
Thanks
Vincent
When Comparing the Message between IIGS and IIC :
It seems I have a bytes shifting by 2 (which is not on my side)
In bold red the command 0x85 which as per the documentation the Init message
IIC. 0000: DF 9F E7 F9 FE FF C3 81 80 80 80 81 A0 C0 85 82
IIGS 0000: F3 FC FF FF FF C3 81 80 80 81 85 C0 85 82 90 85
For some reason the IIGS is not using the same type of message !!!!! WTF!
I need to reread the documentation I must miss something !
any clue someone ?
Vincent
Screenshot 2024-12-15 at 21.59.42.png
Sorry, Vincent, I do not have any SmartPort device and my remaining Apple IIc lacks the IWM - I desoldered it for my reverse engineering work.
I forgot the Apple IIgs totally. I don't have one as I think it's not a "real" Apple II, but this is only my own snarky opinion. IMHO, the IIgs is an entierly new design which seeks to emulate the earlier Apple II family members, using its "Mega II" custom chip, but, according to critics, does not fully achieve that lofty goal of full compatibility. Not having and not wanting a IIgs I still dare a guess that the fallacy with this whole approach is that they assume that the 65C816 can faithfully emulate a 65C02, but even if it is so, this is no NMOS 6502 which is in the earlier Apple II family up to the IIc.
As far as I'm concerned, any "Apple II" not having the "unofficial" opcodes can't be "fully compatible" with ALL the legacy Apple II software out there, so I dislike and ignore every "Apple II" not having a NMOS 6502. The Apple IIc is the only exception and I hate it for that. But it's my platform to test the IWM substitute in a IWM socket.
Hope in SmartPort matters, others can chime in and help you with your quest. Don't wait for me, I'm not knowledgeabe about SmartPort devices.
- Uncle Bernie
I don't have time right now to decode your messages, but it's helpful to understand that there are two completely different things that Apple called by the same name, "SmartPort". The first is a machine-language interface (MLI) built into ProDOS which provides block read and block write functions to applications. This API can be connected to a driver for any block device: a network file server, for instance, or even a Disk II 5.25" 140KB floppy disk.
The second item named "SmartPort" is a hardware protocol for communicating with intelligent peripherals over the Disk II (or later, IWM) floppy interface. Besides regular "dumb" floppy drives that the FDC controls directly, there can be drives with their own processor and internal firmware, communicating back and forth by sending data packets. The UniDisk 3.5" drive was the first of these, and it needed to be intelligent because the native data rate of a 800KB floppy disk is higher than the Disk II or 1 MHz 6502 can handle. The later Apple 3.5" drive, plus the FDHD drive, along with all of the 5.25" drives, are "dumb" devices. Apple did not release any "intelligent" devices for the Apple II series after the UniDisk 3.5", but there were some third-party hard drives, and now retro floppy emulators can use the protocol.
May I ask how many Apple2 software titles used illegal 6502 opcodes? On my opinion you cannot name more than 5...
some updates on my Smartport investigations :
I have figure out why I have a gap between IIG & IIC on the Smartport Protocol: there is no GAP ;) like always my side of the equation was wrong.
The Smartport protocol is issueing
5 x 10 Bits sync which is giving 5 Bytes and the 6th byte is C3 (and the last always C8)
The first issue was that the WR_REQ (Triggering the start of the write) can be overlapping exactly the first bit of the sync & thus you are missing the first Sync Bytes.
To be able to manage the incoming request, only starting from the C3 Bytes can accurately work
Everything that is before the C3, the sync bytes, can fluctuate a lot based on where you are with the internal interrupt and main loop,
The second issue is related to the timer and this one is more complex (and I do not fully understand why).
One timer is triggered with a period of 4x96-1 = 383 (96 Mhz to have 4us ) and a pulse of half 2x96-1. This enable the timer to take the exact middle of the write pulse. This timer is retriggered or extended every rising edge on the WR_DATA pin to do a resync.
For some reason when the period is 383 it is just a bit too long compare to the Apple II that is working at 1,024 Mhz and it is causing a gap in the bit sequence with 1 or 2 bit missing.
There is no issue with a period of 378 (4us at 1.024 Mhz is the equivalent of 375 pulse on the STM32 at 96 MHz)
With a period of 383, the incomming message is :
Screenshot 2024-12-17 at 17.37.04.png
With a period of 378 : the incomming message is :
Screenshot 2024-12-17 at 17.37.20.png
The later one is perfectly formed and no bits are lost with the MSB that should be 1
With this, I was able to receive the 4 init messages for the 4 virtual devices.
The implementation of the Smartport by SmartportSD arduino project is IMHO wrong.
I am done yet, still make good progresses
keep you posted
Vincent
Quick update,
on the IIC I was able to run TOTAL REPLAY via Smartport implementation.
It is not working on IIGS, because I have the same timing issue as for the IIC but not solved yet.
Is there any timing difference, between IIC & IIGS ?
Using DISK II it is quite easy because resync is done every rising edge on WR_DATA and there is not more than 2 consecutive zeros (not too often).
Is there a way to keep the sync when data is 0x80, 0x80 meaning 1000 0000, 1000 0000. ?
Do I miss something ?
thanks
Vincent
Ok good news, I was able to load TOTAL REPLAY on a IIGS using the Smartport. The issue with the timer is the same, it needs to be below the actual IIGS frequency
Now I need to finalize test,
But it means that this STM32 will work on II+,IIe,IIc, & IIGS with 32 MB Images ! ;)
If you plan to use REV1,REV2 of the Board with a IIGS, The circuit trace between PIN 5 & 7 on the IDC20 needs to be cut (IIGS use PIN7 as /DISK3.5 instead of GND).
Vincent
Smartport is emulation is fully working on IIGS (Load og GSOS) and on IIC.
I have built a SmartDisk II card https://github.com/btb/SmartDiskII for Apple IIe to support Smartport, it is like a Liron card I guess.
When I plug my emulator it is not working.
Have someone one of these card working ?
Thanks
Vincent
This is great. Please update github with a release?
I am doing some test with the bootloader and I will publish a new firmware version within the next 48h
Merry Chrismas to all
Hey Vincent,
I'm making good progress with my hardware and have uploaded the first changes to my fork. I am also trying to keep up with your rapid development :)
In the current software version on GitHub, mounting does not work after the yes/no query. DiskIIUnmountImage() is not called when going back after mounting and the flag flgImageMounted is therefore not deleted, which is important for AB switching. I have added a sysReset call when the SD card is removed.
Greetings from Berlin
Joerg
IMG_20241221_170659.jpg
I do, works fine with a SmartPortSD or FujiNet (although only in SmartPort mode, can't support both Disk II and SmartPort at once). I'm waiting on some BlackPills and should be able to help test when they show up.
I have published version 0.79.1 with Smartport emulation (early beta)
in the config select the right emulation
in the sdcard put file with name like vol0x_[what ever].PO (x from 1 to 4);
I did this, but how to activate it? Do I need to hook up additional signals to the DB19 on my V1 board?
Also, what does this mean?
Well, working on the Smartport protocol, be careful on the IIGS Pin 4 is not grounded but -5V and the SmartDisk is following the DISK II interface so YOU NEED TO CUT THE GRND TRACE BETWEEN IDC PIN 5 AND PIN 7. This will fixed in REV 3
If I cut the line between pin 5 and pin 7, I get no more LCD display because ground to that connects to pin 7. I can fix this by cutting the trace there and routing to pin 5 instead, leaving pin 7 unconnected.
Hello Rittwage,
A new option is available in the config :"Emulation type" and you can choose between DISK II, Smartport HD or DISK3.5.
The latter is not available right now, I first need to finish the previous mode.
Then in the config menu you can choose among the 4 possible disk images which one to boot
If I am not wrong PIN 4 on IIGS (DB19) is connected to pin 7 IDC, it means that on rev 1, pin 7 needs to be isolated and GND rerouted to the Oled display.
Let me know if it does work for you
I've got that fixed. I don't see how to choose the vol01_xxx.PO file, though. I can select it in file manager, but it doesn't boot. I don't see where to choose it in the config menu.
Does it need 4 files to exist?
That is my fault I am not clear enough
you put the vol0x_yyyy.PO at the root directory and it will load the vol01 first and then vol02 and vol03 and last vol04
you can choose which to boot with the index in the config
Hello All,
I need a bit a help on finishing the writing part,
When using Locksmith with disk copy or cerify , I pass the test very easy, because it write full track
When I try to init a disc I have a I/O error and using the log I can see that 32 piece of track are being written
Quick question:
- When do I know that writting of a track is finished ? outputting to SDCard takes time
- What is exactly doing the init function from a disk layout content ?
Thanks
Vincent
OK, I got it to work, but I don't see any index setting anywhere.
Success booting Disk II on a IIc with a disk switcher to allow external disk booting. Also got Total Replay working in SmartPort mode. Nice work Vincent.
PXL_20241227_233630808.jpg
You can only deduce that a track is "closed" when the computer sends a seek command to a different track.
The function of the INIT command is described in The DOS Manual. It does the following things:
1. Formats the disk, writing the volume number given to every sector header
2. Creates the Volume Table of Contents (VTOC) on track $11 sector $0
3. Writes DOS to the 35 sectors from track $0 sector $1 to track $2 sector $3, and the boot loader to track $0 sector $0
4. Creates a file of type 'A' named by the file argument, and makes it the greeting program
5. Writes the track/sector list for that file, and updates the VTOC, and writes the directory to track $11 sector $f
So if you are watching the Disk II port with a logic analyzer, that will all be happening. What is simpler is to send just a format command (step 1) to RWTS. From the monitor, type this program:
c00: A9 0C A0 0A 20 D9 03 60 00 00
C0A: 01 60 01 00 00 00 20 0C
: 00 20 00 00 04 00 00 60 01
C20: 00 01 EF D8
and run it with "C00G". This creates an IO Command Block specifying the format command and hands it off to RWTS. After this the disk will be formatted but blank (no DOS, no VTOC, no directory).
Not as cool as @Joergschne work, but keeping with the $10 BOM target this is my current thinking. Bumped up to a 1.54" OLED (~$4) to be able to fit a full size SD card slot for easier handling of the media. Moved to a single rotary encoder for up/down/select and one tact switch for back. Dropped the buzzer size down to 9mm to fit. Could also be produced with a 1.3" OLED (~$1.50) and MicroSD card slot tucked under it as a smaller/cheaper option.
AppleIIDiskIIStm32F411-proto1.JPG
Had a chance to test this in my IIe with a SmartDiskII card. Disk II mode worked only when you forced the card mode via JP8. In Smartport mode it started to boot Total Replay, but hung a couple a times and could never finish the load. Same setup worked fine booting Total Replay from a Fujinet.
This is with Rev2 hardware patched to Rev4 specs running v0.79.1, so Pin 12 is connected to B8. The SmartDisk II card expects that to be pulled high to 5V to select Disk II mode.
Thanks Hideehoo,
Smartport will be fixed to boot total replay,
Softsp firmware is starting sometime with C3 during the sync bits... do not ask me why.. C3 is expected to be the start of the message bytes.
So I patch the firmware (Smartdisk Emulator to handle this case), in rev 0.79.2 it should work.
When you say : " The SmartDisk II card expects that to be pulled high to 5V to select Disk II mode." you mean that if not pull up I can not have the Smartport to work or the Disk II ?
thanks
Vincent
I wonder if you could also add a 6-pin header for an Micro SD card board like this one: https://www.amazon.com/dp/B07BJ2P6X6?ref=ppx_yo2ov_dt_b_fed_asin_title
Soldering it is much easier than soldering the tiny Micro SD card slot.
Be careful with those modules. They don't tri-state MISO when CS is false so they don't play real nicely on the SPI bus. (TBH, I haven't looked at the schematic for this board in a long time, so I don't remember if anything else is on the SPI bus.)
I do not use SPI for the SDCard but Quad SDIO, not sure that the MicroSD Board works in that case
Vincent
I would agree with Vincent; the microSD module doesn't hook up all the data lines needed for a Quad SDIO interface.
You could use a passive breakout board like this, https://www.aliexpress.us/item/2251832601205156.html. I did something simlar with a SPI only version on my through-hole Fujinet Atari design.
TF-Card-Breakout.JPG
If the concern is about soldering the SMD connectors on the card, you could also move to the full size SD card in this form factor. https://www.aliexpress.us/item/3256805779248826.html
SD-Connector.JPG
They are even easier to solder than the MicroSD ones, which personally I've never had any issue with provided you still have a steady hand. That's the connector I have tucked under the larger OLED in the design variant I posted a few messages back.
These are based on microSD to standard SD adapters which are a dime a dozen:
Micro_SD_adapter_A.jpg
Micro_SD_adapter_B.jpg
The advantages other than being cheap are: no soldering problems (easy hand soldering) and you can use a 90 degree bent pin header to make them sit as a cover over other SMD components on a PCB. This saves PCB space.
- Uncle Bernie
Hello Guys,
I continue my effort to stabilize the writing part of the SDISK II.
I am facing an issue with the timer and the interrupt.
Basically I have from time to time an additonnal bit due to dephasing of the Timer pulse period.
In a nutshell,
Timer 2 is set to have a period of 4x96-1 pulse (96 Mhz -1 x4 for 4us)
I use Count and Compare to trigger an interrupt at excatly half of the period to be in the middle of the WR_DATA pulse (2us)
To keep the timer2 synced I reset the timer every rising edge of the WR_DATA pin
For some reason, I have bit added to the stream without any rationnal.
So quick question on my end:
- Does someone understand what is hapening ?
- Do I need to resync the timer or can I consider the 4us accurate along the datastream ? If accurate enough I can try to only trigger the timer at the first rising edge without reset
Thanks for your thoughts
Vincent
Breakout boards are also available for full size SD cards. I chose that for my build of this project because I feel it's less fiddley inserting and removing the larger cards. I used https://www.sengoku.co.jp/mod/sgk_cart/detail.php?code=EEHD-47ZR which has all the pins and card presence sense lines brought out, but probably something like this https://www.amazon.co.jp/-/en/SD-MMC-Card-Breakout-Board/dp/B0DSBVWKYP would work, too. Not sure. Just be careful to compare against the schematic. As people say: this project talks to the cards using the SDIO interface protocol, that's a faster 4 bit parallel protocol, not the SPI serial protocol, so you need a break-out board that includes connections for the D0 through D3 lines. If the board has a small number of pins and two are labelled MISO and MOSI, then that's the wrong wiring scheme and won't work.
Hello All,
Just a quick update, I have publish on github the revision 0.79.2 that is bringing more stability on woz writing.
The issue was not an isolated bug in the coding:
- When DOS3.3 is formating a floppy with the INIT HELLO command, it split the writing in sequence per sector and within sector between sector header and data.
Thus between 2 sequence you can not trigger in background even with DMA the writing otherwise the interrupt for receiving the next sequence get corrutped
It means that you should a record on a pending write before moving the head of the drive (and after a idle period).
The second issue was using the ST HAL (High Level Driver) which create unpredicable overhead on the timing process with the ASSERT that is everywhere.
I have done the following test:
- LockSmith 6.02B Fast copy : OK
- Locksmith 6.02B Backup: OK
- Locksmith Certify : OK
- DOS INIT : OK
Please feel free to test the last release and give me some feedback
Thanks
Vincent
Hello Vincent.
Just a question, in this version is it possible to save a simple program using DOS 3.3? I am using WOZ 2 and applying the SAVE command, but it returns Write Protect.
Thanks,
Daniel.
Hello Daniel, is the woz file write protected ? this can be the issue.
I will do some tests tomorrow
Which version are you using btw ?
Vincent
v0.79.4 is out fixing issue on Menu config and SmartPort Display
Hello Vincent.
I can confirm now that the problem was the protected WOZ file.
Now I can write several basic programs in WOZ 2.0.
Thank you for your hard work.
*The forum system presented an error and ended up duplicating two previous posts.
Very good, thaks for the feedback.
I have detected an issue with the PRODOS init process, I will need to further investigate
Keep you posted
Vincent
I have updated a few of the boards I have built with v0.79.4 and I can verify that SAVE of Applesoft program at least works under a DOS 3.3 image converted to .woz. I have not yet tried ProDOS, but I will do so as well as some other things.
I'm really excited to see write functionality become more mature for this device. I will be super stoked when writing to .dsk and .po images and maybe .nib is working. That will really make this project awesome.
I noticed there is a new v0.79.6 on GitHub. What needs to be tested?
Hello All,
I have uploaded the firmware v0.80.1.
The Smartport PO write process finally works ! as well reading process is optimized !
more to come soon !
Vincent
Nice, I will pull again and update a couple of the boards I have built and give it a try!
Hi Vincent,
Thank you so much for the endless effort you share with us. I was a bit confused about the WR-REQ signal, which according to the controller schematic is not inverted, but on the drive schematic it is. It appears to be an inverted signal. I have now adjusted this in my wiring diagram. I initialize a new fork due to the many changes in the meantime and then insert my changes again. The only important thing is to adjust the display initialization and implement the control of the drive switching ( /AB at B8 ). The display works without any firmware changes recommended by the manufacturer, but is then rotated by 180 degrees. Maybe you would like to support me with the implementation of the rotary encoder in your firmware?
KR
Joerg
Bildschirmfoto 2025-02-09 um 14.55.18.png
Bildschirmfoto 2025-02-09 um 14.04.21.png
Hello Joerg,
I am very impressed by this work, well done !
Of course, I would be happy to integrate the rotary encoder, let me look at your code.
Regarding WR_REQ, it does not mater if it is inverted or not, I managed it internally as an Input GPIO, I check as well the status of /DEVICE_ENABLE.
Vincent
I am starting the 3.5 DISK emulation.
I need to understand the way it works as Phase0 - 4 are not working the same way as for the DISKII.
Is there somewhere a description of the internal Disk3.5 and as well the timing ?
That would help me a lot
Thanks
Vincent
To be more specific,
I have read the IIGS firmware specification related to SMartport and 3.5 Disk.
Quick questions on my end for expert:
- Is the IIGS Disk 3.5 drive is managed like a classical smartport device ?
- I see block management, does that means that there is no head move management and this is done internally to the drive ?
Thanks
Vincent
Ok after reading some doc
I understand that there is 2 types of Drive:
- 3.5 non smartport
- 3.5 Smartport
When using non smartport drive : https://llx.com/Neil/a2/disk is a good summary of the way to manage it
Regarding IWM, Do I understand correctly when dealing with Q7L it is the WP_PROTECT PIN on the Disk drive ?
Thanks
Vincent
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