Hi fans -
I've been in search of a way to increase the RAM of the Apple-1 to a useful amout I need for testing more complex software (currently under development) on it. Emulators like POM can't help as my work involves some extra peripherals not being emulated.
It's not easy to add robust RAM to the Apple-1 due to the quirkyness of its bus timing. Woz did not use the PHI1, PHI2 signals offered by the 6502 but chose to make "fake" PHI1, PHI2 signals with TTL logic. This may have been the stumbling stone which back in the mid 1970s made Chuck Peddle furious, leading to Mr. Peddle claiming that Woz had no idea about proper microcomputer design (or along these lines). But this is another story. Fact is, MOS Technology and all epigones who produced 6502's put out elaborate "Application Information" pamphlets which showed how it's supposed to be done the "right" way: using PHI2 from the 6502 to gate / time all peripheral and memory accesses. Woz ignored that advice. But IMHO he did know what he was doing as he did chose 480ns for the DRAM /CAS timing oneshot in the Apple-1 and you get this number only when taking the additional timing uncertainties caused by ignoring the "real" PHI1 and PHI2 into account. Was Woz a fool going against the 6502 manufacturer's recommendations ? Hmmm. I leave that judgement to you, dear reader. But keep in mind, if you really work the numbers, you will find that the 6502 bus timing concept is fundamentally flawed and the issue gets worse with faster memories. It probably worked OK in the 1970s with the slower memories of the time being, but in the early 1980s the RAMs had gotten so fast that both Apple and Atari started to use custom ICs for the DRAM timing, based on the fast and accurate master clock in the machine. For Apple, it was the "MMU" seen in the Apple IIe and for Atari, it was the "Freddie" chip seen in their Atari XE lineup, which includes their XEGS video game console.
When I designed the DRAM card, I adopted these concepts, and derive all the DRAM timing from the precise 14.31818 MHz master clock. All PHI1, PHI2 signals are utterly ignored ("all" meaning both the "real" ones offered by the 6502 and the "fake" ones Woz made with TTL gates, as all of them are useless to generate robust memory access timing). I was able to cram the state machines comprising the DRAM controller into a 16R8 PAL (which was available in Y1978). For the development, I use GAL16V8 as the fuse link PALs are rare and very expensive, and can't be reprogrammed. This is how the "lab rat" looks:
It runs very robustly and without DRAM errors, for more than 48h now (it came alive this Saturday). So sorry, no more thorough and longer tests available yet. It seems that the only remaining issue to be solved is which signal conditioning circuit needs to be used to clean up the clock, which looks like that:
This rotten clock won't yield a robust system. Knowing about the problem with signal integrity on the Apple-1 bus, I put a "signal conditioner" plug-in on the card so I can change the circuit which cleans up the clock. The jury is still out if I can do it with passive circuits, or one IC, or two ICs.
If I could do it with one IC, such as a 74xx14 Schmitt Trigger, I could use an SMD and "hide" it below the PAL/GAL. Which would mean that a PCB for the DRAM expansion could be as small as the ACI. And it would plug into the edge connector, to keep the sole "slot" on the Apple-1 useful for a mass storage peripheral (the ACI or my planned Floppy Disk Controller card). This DRAM card would be small enough to fit into most enclosures made by individual builders. Hopefully so. The existence of tightly fitting custom enclosures for the Apple-1 is a big headache for anyone wanting to make expansion cards. Which, of course, must fit in ! And hindsight is 20:20 ;-)
No PCB layout has been made yet. I'd like to see your comments on this work. Would you want to have such a card ? Cost wise it would be below $50 (completely assembled and tested) if I could avoid a multilayer PCB. This, however, would need to route two signal traces between IC pins. No issue for modern PCB manufacturing, but maybe it would look wrong, who knows.
Technical summary: Apple-1 DRAM card based on two 64kx4 DRAMs. Robust crystal oscillator based timing. No adjustments. PAL/GAL can be configured to map the underlying DRAM into any combination of 4k banks (as far as product terms available allow). For the "lab rat" I have chosen to have additional 48 kBytes of RAM from $1000 to $BFFF. This is about as much as you can get. $Cxxx is already occupied by the ACI (and later, the Floppy Disk controller card). In this configuration, $0000-$0FFF and $E000-$EFFF is provided by the two 4k RAM banks on the motherboard. So the Apple-1 in this configuration has 56 kBytes of DRAM. However, for those maverick builders whose DRAM does not want to work, the DRAM card could also be configured to provide all memory by itself. You would just disable the wonky on-board DRAM by jumpering the "W" and "X" signals in the memory decoder patch board to "H". In any case you need to add a single wire on the backside of the Apple-1 motherboard to route the 14 MHz master clock to the 44-pin bus (via the usually uncommitted "S" chip select line in the 74154 patch field).
I think such a DRAM card with a small form factor might be useful enough to attract enough buyers to make layout and manufacturing of a small PCB production run economically viable. For myself, I only need one or two such cards and I won't layout a PCB for that quantity.
Comments invited !
- Uncle Bernie