I have a question. How did various accelerators handle accessing the FDD?
Did they adapt to the DISK II's clock speed, utilize the 6502's main processor, or did they disable it?
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Anything that accesses the hardware or even certain memory ranges, must be slowed down to the original 1MHz.
That's why some operations are accelerated and some are not.
Thanks for your reply.
I understand that I need to synchronize with a 1 MHz cycle for I/O and RAM accesses.
However, I wonder what the impact would be if I limited the number of cycles to one for each FDD instruction.For example, the sta Cxxx instruction executes in 4 cycles, but there would only be one.
The next cycle could perform an I/O read.
I understand that I would either have to write a new FDD read routine with delays or force I/O accesses to take the same number of cycles for each instruction.
IMHO, the simplest and most robust way to deal with this problem is to let the 6502 clock fall back to 1 Mhz whenever the spindle motor is running. This only requires one flight wire from the 556 timer on the DISK II slot card to the PLD (or whatever IC) which generates the clocks. No software rewrites needed.
Following the "KISS" principle.
- Uncle Bernie
A caching accelerator like the Zipchip needs to slow down for all RAM and I/O. The transwarp (not the transwarpGS) does things differently. It has 256 of RAM on the card and on startup it copies ROM over to it’s RAM then it uses it’s RAM in place of the motherboard RAM and the first 2 banks on the Aux card. The motherboard RAM isn’t used at all. As an experiment I once ran a transwarped IIe with no motherboard RAM installed.
Wayne, with all due respect (you have helped me a lot throughout the decades, thank you!), you are making a mistake now, an apple2 motherboard must have worked without the CPU with transwarp card, but motherboard RAM must have been installed, otherwise the apple couldn't have output composite video. Probably the bus sooping VGA cards can work in such configuration and you used one. I don't need, like and have any of those VGA cards to confirm this, but my engineering thought tells me it should work.
@UncleBernieUnfortunately, my circuit isn't based on the 6502, but rather on its emulation. Specifically, it emulates several different 65C02, 65C816, and i8080 chips. It can also execute ARM code or even mix them in a single program.
But thanks, because you gave me an interesting idea.
I don't want to slow it down too much, and I'd still like to have faster access to other cards, so perhaps it would be enough to programmatically track the drive's power-on/power-off and make changes to the emulation while the FDD is running.
@Wayne
But wouldn't a solution like the transwap affect software compatibility?